[SOLVED] Verilog output viewing

[surajdash]

Can someone tell me how do i see waveforms of signals that are neither inputs or outputs of a verilog code but are used in the program in the modules.

 

[vipinlal]

Which simulation tool are you using?

 

[surajdash]

Which simulation tool are you using?

Xilinx 12.3

 

[vipinlal]

Check this doc:
**broken link removed**

browse down and you will see how to see the internal signals in xilinx ise tool. I will copy paste the relevant part here:

While running simulations on your designs, you will probably find the need to be able to view internal
signals and their values as the simulation runs on via the timing diagram. To get this working, draw your
attention to the left most panel when ISim opens, called “Instances and Processes”. Here you can view
all of the running instances of designs and processes within each design in your current test bench. To
get the items from the decoder to show up in your timing diagram, click the down arrow on
“counter_tb”, followed by the down arrow on “uut”. This will show you all of the processes running
inside of the design as well as internal signals used within. To display an internal signal in the timing
diagram, highlight one such as “count” and right-click, followed by Copy.

 

[surajdash]

Thanks a lot vipinlal.