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Hello, I am making a CMOS to CSI2 bridge application with Lattice Crosslink FPGA. When I looked at the differential output Dphy Clock ports, I saw that they were not at the same voltage. I can see the calculated frequency and 90 degree phase shift apart from the voltage difference. What is the...
As @FvM said these transistors (Fmmt417) have no pnp series. I simulated the image I shared and I'm getting symmetrical output. All I want is to design them as a stack, not a marx generator-based cascade.
Could you elaborate a little more, sir?
1669014048
It doesn't drop to exactly 0 V, it...
Finally found an example. As far as I understand, all the pins that output CMOS33 are. As you said, it has connected the pixel clock to a pin that supports the clock input feature. I am sharing the source link, anyone who needs it can take a look. Thank you for your interest. Have a nice day...
I meant my workload.
I need to input the parallel camera pixels to the FPGA with "Pixel to Byte IP". My camera outputs 3.3V CMOS. I was not sure which pins I can use in Crosslink. I have the Crosslink LIF-MD6000 Master Link Board. What I'm wondering is,
1) Can we use differential CMOS inputs...
I looked through the documentation but couldn't find it, unfortunately I also have a time problem. Can you tell me how is the pin configuration of any IP? It can be in a link or sample code.
Hello, I will use "CSI-2/DSI D-PHY Transmitter Submodule IP" for Crosslink FPGA in Lattice Diamond. I want to know the pin setting of this IP, but I couldn't find which pins the IP uses and IP pin constraints. He gave an example as follows, but I couldn't see the source of it and I wonder how it...
Hello everyone ,
1) In the FPGA world, there is the concept of IP and when I use these IPs, I cannot feel myself as a designer (What I am talking about is not ASIC). Is this feeling wrong? In the business world, do people write the design themselves or do they use IPs?
2) For example, we need an...
Hello, I have a thermal camera (640 x 512) and it outputs 8 bit RAW and YUV 4:2:2 in parallel. It also has LVDS output. First I tried to convert these outputs to CSI-2 but ran into some incompatibility problems. My goal is just to pass this pixel data to jetson nano. What ways can you suggest...
I am trying to make a CSI 2 Transmitter with Lattice Crosslink, but the reference designs are not visible on Lattice's website. Anyone have sample code or reference design?
Hello Rajinder, I recommend look at the this blog,
https://www.electronicdesign.com/power-management/article/21801509/reversepolarity-protection-in-automotive-design
Basically it is enough you attention "peak current and voltage". Also don't forget the TVS diode option for voltage spikes.
Hello, I want a status to be maintained for a certain period of time. For example, assigning the output to a certain value for 100ns. I thought of a method for this, but I don't know if it makes sense. There will be a counter module and it will count continuously until the reset signal arrives...
Hello, I see sample codes like this. It got a little weird. Each mipi_clk will have rst_cnt <= 0, but rst_cnt <=1 if the necessary conditions are met. Aren't these processes parallel?
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