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CSI Dphy Clock Voltage difference

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stark43

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Hello, I am making a CMOS to CSI2 bridge application with Lattice Crosslink FPGA. When I looked at the differential output Dphy Clock ports, I saw that they were not at the same voltage. I can see the calculated frequency and 90 degree phase shift apart from the voltage difference. What is the reason for this and does it cause problems?

Dphy Clkp : 22mV
Dphy Clkn : 32mV
 

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