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Recent content by sobella1923

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    Read and Write operation on DDR via EDK

    hi im new to this Xlinx EDK tool. i have been trying to access the DDR memory of my virtex 4 ML-403. i have interfaced the memory with microblaze processor successfully. i dont know how to perform basic read/write operation using EDK. any help would be appricaited.
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    [SOLVED] not (~) a single bit in an array in verilog

    im need to take a not of a single bit in a array of 16. input [15:0] dat1 =16'b0000001000000001; what i need is output [15:0]dat2=16'b0001001000000001;
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    [SOLVED] Negative value in Verilog

    its not working....it assigns 1 again not -1
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    [SOLVED] Negative value in Verilog

    is it possible to assign a negative value to a reg in verilog. I have reg [11:0] ptr; instead of 0 i want to initialize this vector with -1 ptr=-1-1-1-1-1-1-1-1-1-1-1-1 how can i do that???
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    DDR size in vertex 4???

    hay!! i cant figure out the size of block in this specific DDR in vertex 4, can anyone tell me what is the block size this DDR Vertex 4 contains 64 MB of DDR SDRAM using two Infineon HYB25D256160BT-7 (or compatible) chips (U4 and U5). Each chip is 16 bits wide and together form a 32-bit data...
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    [SOLVED] even parity using verilog code!!!

    im initializing the values of data below thats why the initial block.
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    [SOLVED] even parity using verilog code!!!

    hi! im trying to write a verilog prog that inserts an even parity at the end of the data. i need some help in debugging it. thx module parity(data,vparity); input [4:0] data; output vparity; integer i; reg [4:0] data; reg parity; reg vparity; initial begin assign data=5'b10100; assign...

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