[SOLVED] even parity using verilog code!!!

[sobella1923]

hi!
im trying to write a verilog prog that inserts an even parity at the end of the data. i need some help in debugging it. thx

module parity(data,vparity);
input [4:0] data;
output vparity;

integer i;

reg [4:0] data;
reg parity;
reg vparity;

initial
begin

assign data=5'b10100;
assign parity = 1'b0;

for (i= 0; i < 5; i = i + 1)
begin
assign parity = parity ^ data;
end

assign vparity={data, vparity};
end
endmodule

 

[TrickyDicky]

why have you put this code in an initial block? why not in an always block?

 

[sobella1923]

im initializing the values of data below thats why the initial block.

 

[TrickyDicky]

well for a start, data is an input, so you cannot assign anything to it.

 

[rberek]

 vparity = {data,^data};

No loops are required, just use the unary XOR operator as above.

As well as fixing what TrickyDicky said.

r.b.