[SOLVED] not (~) a single bit in an array in verilog

[sobella1923]

im need to take a not of a single bit in a array of 16.

input [15:0] dat1 =16'b0000001000000001;

what i need is

output [15:0]dat2=16'b0001001000000001;

 

[imbichie]

in VHDL the above thing will be like this

dat2 <= dat1(15 downto 13) & (not(dat1(12))) & dat1(11 downto 0);

 

[dave_59]

There are several ways you could do this

One way is

always @dat1 begin
               dat2 = dat1;
               dat2[12] = ~ dat1[12];
          end

Even though you assign dat2[12] twice, only the last assignment wins. Synthesis tools only synthesize the last assignment.

You could also do

assign dat2 = {dat1[15:13], ~dat1[12], dat1[11:0]};