[SOLVED] Negative value in Verilog

[sobella1923]

is it possible to assign a negative value to a reg in verilog. I have

reg [11:0] ptr;

instead of 0 i want to initialize this vector with -1

ptr=-1-1-1-1-1-1-1-1-1-1-1-1

how can i do that???

 

[mrflibble]

reg signed [7:0] a_number_is_not_a_vector = -1;

 

[sobella1923]

its not working....it assigns 1 again not -1

 

[mrflibble]

I have a hard time believing that. How did you come to that conclusion?

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Also, you did notice the difference between a vector and a number, right?

I just gave you a single 8-bit signed number. No need to add the extra confusion of a vector of signed numbers if the problem of the day is "How do I work with signed numbers in verilog".

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Some examples using signed: http://www.asic-world.com/verilog/verilog2k1.html