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if you are considering to increase the minimum pulse width of the PFD you can still use additional inverter delays, therefor you can avoid dead-zone non-ideality by increasing the reset path delay. what I was mentioning is about minimum pulse width.
Place even number of inverters as a delay element in the reset path of PFD. Then you'll have a long reset delay due to the propagation delays of inverters.
This error in steady state is called as "phase offset".
It is because of the mismatch of charge pump and gate leakage of the loop filter. If gate leakage is not calculated in your model then it is probably because of charge pump mismatch.
If you are using the transmission gate the delay is determined by the current of transistors which drive your transmission gate. For proper sizing, it is better considering the current that will pass through your transmission gate.
It is better to use the same pmos/nmos ratio as other cmos...
Charge-pump might have mismatch in its up and down current networks, or the PFD is not functioning properly for the input phase difference. You may check the outputs of PFD and the charge-pump seperately and together.
pll voltage vdd
If your feedback divider does not work, pll may fail to correct control voltage, and no feedback coming means the vco is not oscillating which moves control voltage to VDD. At the instance of strange behavior please check the output of the feedback divider. Regards.
Sorry, I do not have any chapters of the book as an electronic copy. I read it once in hardcopy. You can check www.cmosedu.com for more figures and circuit files. Regards
This is the circuit from the book. You can find all the images from www.cmosedu.com
For the circuit: It looks simple, works with very small Vgs-Vt due to resistor and the body effect of M5R. But you need to take into count the additional resistor noise. This is a simple one, hope it works for you.
There is a V2I circuit used for linearization of VCO characteristic shown in CMOS of Jacob Baker. Please check PLL chapter of the book and you will find the V2I circuit out there. If you cannot find it you can leave a message.
linear vds control
You can increase W/L ratio for less voltage drop (Vds) of each cascode device and also use a low voltage cascode current reference to get a minimum voltage of 2Vds(sat) for each cascode pair. You should check Page 273 of Gray&Meyer 4th ed. as an example reference circuit.
Open rf018.scs in your library folder, there you will find bsim parameters or just run an operating point analysis in cadence and print device parameters to results window, there you can also find related MOSFET parameters.
You can calculate mobility using bsim3 or bsim4 parameters. also Cox is Eox(E=epsilon) divided with Tox (oxide thickness). You can grab a textbook using BSIM models to calculate those parameters.
You can use winspice for spice simulations. I suggest v1.05.07 for simulations with bsim3. v1.06...
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