question about dll design.

[godspeed.w]

I design a kind of dll (pd + cp + vcdl ).
my question is when the dll is locked there is about 1ns error between reference signal and feedback signal and the up signal is 1ns width but vctrl is stable.
who can tell me why ?3x

 

[smoked]

This error in steady state is called as "phase offset".

It is because of the mismatch of charge pump and gate leakage of the loop filter. If gate leakage is not calculated in your model then it is probably because of charge pump mismatch.

 

[godspeed.w]

thank you very much.
I have a new question about it
the dll can enter locked state and phase offset is very small maybe ps level and then the dll left locked state and then the vctrl is not change.

 

[godspeed.w]

who can tell me the delay time requirement of vcdl
3x