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Hi All,
I am having one counter which is free running and not resetable in VHDL.
Problem is during simulation it its value is 'x' because of non reset control.
Can any one knows what code can be implement in synthesizable code to force initial value to 0.
does --synopsys translate off and on...
If a design has both negative-edge triggered flip-flops (active clock edge is falling edge) and positive-edge triggered flip-flops (active clock edge is rising edge), it is likely that half-cycle paths exist in the design. A half-cycle path could be from a rising edge flip-flop to a falling edge...
The hold checks do not require the clock jitter to be included in the
uncertainty and thus a smaller value of clock uncertainty is generally specified
for hold.
HTH,
Shitansh Vaghela
Fortunately there is no document, the easiest way.
First understand functionality of mat-lab code and then think in terms of hardware and write HDL code accordingly.
Regards,
Shitansh Vaghela
Simplest way is FSM.
Optimal solution is also available, you have to approach your self and if there is problems, there are n number of experts available here!!!!!!!!
You can do some thing like this,
1. One instance of your code.
2. Design decoder circuit for chipselect and other signals, since only once chipselect will active at a time this will work.
3. To optimize mux and decoder logic you can use generate statement with if..else construct. (This is...
In RTL compiler there is one command which sets high priority for DRC rules for synthesis.
I think same kind of command will be there in DC too, In one word you have to run synthesis with DRC check as high priority.
HTH,
Shitansh Vaghela
I would suggest to think your self and write your opinion here, that is best way of learning if you are wrong then you will be corrected....
This is very simple think over it..
Here one question, how clock will be enabled again, since once enable pin is activated (o/p of xor), then it will enable pin of gated clock and enable pin of gated cell (o/p of xor gate) will be activated, how to make enable deactivated again with this circuit so that clock will again...
Further in this question, can any body tell in case of gated cell for clock, which constraint has to give for gated enable pin, for synthesis and Timing Analysis???
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