[SOLVED] Trigger detection circut..!

[vjain419]

hi..
i need verilog code for trigger detection circuit..clk,trigger_in,reset_n are input..and count_en,count_init,latch_count are output.

when trigger pulse start count_init get asserted and when it stop latch_count is assereted..and between start and stop time count_en is asserted...

i need sync_trigger pulse so i use 2 d-ff so i got sync_trigger...
i wanted out in this style..


i know i can simply use posedge of clk and sync_trigger but for my design i can only use posedge of clk so i wanted some combo logic to get it done..

that drawing is just example is mspaint so sorry for inconvience

regards,
vinay

 

[mrflibble]

Is it just me, or have I seen this homework assignment before? I think it might have been one year ago or so...

 

[shitansh]

Simplest way is FSM.

Optimal solution is also available, you have to approach your self and if there is problems, there are n number of experts available here!!!!!!!!

 

[vjain419]

thank you i got solution