VHDL code for initial force in synthesizable code

[shitansh]

Hi All,

I am having one counter which is free running and not resetable in VHDL.

Problem is during simulation it its value is 'x' because of non reset control.

Can any one knows what code can be implement in synthesizable code to force initial value to 0.

does --synopsys translate off and on will help?

what is similar in VHDL like "initial in verilog"

Thanks & Regards,
--
Shitansh Vaghela

 

[TrickyDicky]

if you are getting 'X', it means you have a problem in the code - usually a signal being driven from two sources.
If on the other hand, it is 'U', yes, it needs an initial value. Inital values are given when you declare the signal, otherwise they always take the leftmost value of the type. So if you were using a natual for the counter, it would initialise automatically to 0.

signal a : integer; --initialises to 2^-31
signal b : natural; - initialises to 0
signal c : integer range 0 to 31; - initialises to 0

signal d : unsigned(7 downto 0) := x"00"; -- initialises to "00000000"

 

[dftrtl]

Initial Block is not synthesizable. Do not worry about simulation results see how it behaves on FPGA

 

[TrickyDicky]

initialising signals IS synthesisable (with more modern compilers anyway). It will give the registers their power up state, if the signals infer registers.

 

[lucbra]

And I would worry about the 'X' value. Any undefined state (x,u, '-', ..) should be verified in depth