Design Compiler and Clock uncertainty constraint

[mouzid]

Hi, I'm using design compiler for synthesizing a digital block but I have to setup contraints for that. I use a 100MHz clock to synch my circuit and I set clock uncertainty to 10% of the clock. In my undertanding I have a confusion. I really dont know if this mean ±1MHz clock or ±0.5MHz of the clock.

 

[shitansh]

You can individually give constraint for setup and hold. using
set_clock_uncertainity -setup , set_clock_uncertainity -hold command

if you give 0.5 ns for setup and 0.5 ns for hold uncertainty then total uncertainty in 1ns, if you have not specify setup or hold in uncertainty then same value would be for setup and hold.

HTH

 

[mouzid]

If I dont use set_clock_uncertainity -setup and set_clock_uncertainity commands and I set uncertainty to 10% will the total jitter tolerance be 1ns or 2ns ?
(Fig A/ or Fig B/ ?)

 

[useless_skew]

If I dont use set_clock_uncertainity -setup and set_clock_uncertainity commands and I set uncertainty to 10% will the total jitter tolerance be 1ns or 2ns ?
(Fig A/ or Fig B/ ?)

Fig A

 

[chandrakanenator]

Shitansh,
I understood what is jitter,skew,setup margin and latency.But can you tell how to calculate the input and output delay constraints for logic synthsesis.I am getting the formulas evrywhere i browse but i didnt get any explanation for that.

 

[shitansh]

Write down formula for which you need explanation..