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Hello, I have some practical questions on the layout of mixed-signal circuits. I'll appreciate even if you only answer one of the following questions.. :idea:
1..:arrow: When drawing the layout of a MOS, is it a good idea to put M1-M2 (matel1-metal2) and M2-M3.. contacts directly on the...
Hello,
I want to make a post-layout simulation in Calibre. At the moment I'm extracting the layout with CalibreXRC and looking at the report and placing the parasitic capacitances in the schematic view and simulating. But it takes a long time and I know that this is much simpler with Diva...
Re: Ring Oscillator
Hi dasong,
How do you make a noise analysis? is it pnoise? and what's a good noise performance and what's a bad noise performance? thanks in advance..
Ok i decided to use the first circuit, i only added another pmos transistor parallel to the pmos, with its gate connected to its drain (saturated pmos). it slightly improved the characteristic. still not so linear, but the vco works fine with those inputs anyway..
thank you guys for your help...
Hello Davood and sunking,
I have designed an opamp as you have suggested and here is the circuit schematic and waveform:
**broken link removed**
**broken link removed**
They don't look much different, only it's more linear.. i want it to be rail-to-rail :|
Added after 39 minutes:
And also...
Hello,
I want to generate a complementary analog voltage out of another voltage. I tried the following circuit you'll find in the first link and the in-out characteristic is in the second link. But i want both a linear and a peak-to-peak(almost) variation at the output voltage. What do you...
hmm i haven't.. actually i think that's the problem cause it locks to the frequency of interest with a much different control voltage. but still the pll locks.. the problem is, it's not a simple pll but a clock recovery circuit. so the retimed data is not equivalent to incoming data.. i shall...
I have a PLL working very well with tt (typical) transistors but not with ss (slow pmos slow nmos) transistors. Well what would you suggest? widen the transistors for speed up? I don't have an idea what to do when ss simulation fails..?
Re: [Discuss] What's the most difficult topic in analog/mixe
I think Analog design is itself more difficult then digital design as you have to deal with several different parameters that interact with each other, while in digital, you have 1 or 0 and you're concerned not "how" the node will go...
Re: Ring Oscillator
I have been simulating only the vco itself with a control voltage input. the number of inverters is 5 and each of them have 700fF load capacitance at the output node because frequency of interest is 10MHz and i can't achieve it with only parasitic capacitances. the frequency...
you can use the conventional phase frequency detector consisting of 2 flipflops and an and gate. you can find the information on it in most of the books. when you design digital gates, let's say an inverter, make the pmos 3 almost 3 times larger than the nmos so that you'll have same delays for...
but then if you have nmos pair, input voltage can go upto vdd while for pmos pair this is not possible. so why do we prefer that the input should be able to go down to ground rather then vdd? doesn't the nmos have the same advantage for vdd rail?
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