Why using PMOS at input stage

[vvchan]

In many books, they say PMOS is good to be used in input stage due to its offset and noise performance. I heard about that it is due to its large size and low mobility. Can anyone further explain this?

 

[flushrat]

With same gm, large pmos size => small offset, and pmos in n-well => low noise
Offset is determined by mismatch, and mismatch is proportional to 1/sqrt(W*L). so large size will have small mismatch.
The reason for low noise is:
1. N-well is more clean than substrate.
2. pmos have less 1/f noise because 1/f noise is proportional to 1/(W*L). In addition, holes are far from surface or interface compared with electrons, which means surface defect have less effect on pmos than on nmos.

 

[vvchan]

Sorry, I don't understand. why PMOS in n-well imply low noise? and why larger size imply low offset?

 

[Sezi]

yes, please if you know the explanation, don't repeat the fact, but write why this is so? I'm also interested in a detailed explanation

 

[bsrivastava]

PMOS is good to be used in input stage because of :
a) it maximizes the slew rate (pmos has more Vod, overdrive voltage)
b) flicker noise of pmos is less than nmos (1/f noise)

Apart from it, there are some advantages of having nmos as second stage.

-Bharat

 

[demodb]

noise power is proportional to mobility which is lower in PMOS.
For mismatch a large W is benificiary to mismatch. I'll try to explain it with two transistor in a mirror. Id1=1/2*K1*Vod^2 and Id2=1/2*K2*Vod^2, in a mirror Id1=Id2. So the ratio becomes Id1/Id2=K2/K1, so increasing of W will make the copying less vulnerable to W.

 

[jutek]

"The reason to chose a PMOS input stage comes from the necessity to reduce the influence of the substrate noise. The two transistors are in a N-well and the well is connected to the supply voltage such that any substrate interference coupled via the parasitic capacitance to substrate is decoupled to VDD line."

**broken link removed**

regards

 

[vvchan]

Thank you all of you. It helps a lot.

 

[hrkhari]

In deep submicron technology, PMOS is to have better velocity saturation performance, due to the lower crictical horizontal electric field.

Rgds

 

[evi]

2. pmos have less 1/f noise because 1/f noise is proportional to 1/(W*L). In addition, holes are far from surface or interface compared with electrons, which means surface defect have less effect on pmos than on nmos.

Surprisingly, in TSMC 0.18 it's the other way around, at least that's what the model says. I don't know if it's an error in the model, or if it's real.

 

[Chethan]

There are drawbacks also using the PMOS at the input stage. P channel device generate more thermal noise than n channel device of the same size and same biasing. That is coz thermal noise of a device is inversly proportional to the device's gm.

 

[holddreams]

Ken Martin's book page 231 wrote:

The choice of which configuration to use depends on a number of trade-offs .

First ,the overall dc gain is largely unaffected by the choice since both designs have one stage with one or moren-channel driving transistors,and one stage with one or more p-channel driving transistors.
For a given power dissipation ,and therefore bias current,having a p-channel input-pair stage maximizes the slew rate.This result is seen from (5.19) since p-channel input transistors for the first stage have a larger Veff than would be the case for n-channel input transistors(assuming similar maximum widths have been chosen to maximize the gain).This slew-rate improvement can be one of the most important considerations ,and thus most knowledgeable designers choose a p-chanel input for the first stage.
Having a p-channel input first stage implies that the second stage has an n-channel input drive transistor.This arrangement maximizes the transconductance of the drive transistor of the second stage,which is critical when high-frequency operation is important.As we will see in the next section,the equivalent second pole,and therefore the unity-gain frequency as well ,are both proportional to the transconductance of the second stage.

Added after 6 minutes:

Another consideration is whether a p-channel or n-channel source-follower output stage is desired.Typically ,an n-channel source follower is preferable because this will have less of a voltage drop.Also,since an n-chnnel transistor has a higher transconductance ,the effect on the equialent second pole due to its load capacitance is minimized,which is another important consideration.FInally,there is less degradation of the gain when small load resistances are being driven.
The one disadvantage of having an n-channel source follower is that ,for n-well processes,it is not possible to cnnect the source to the substrate,thereby minimizing the voltage drop.Finally,note that ,for opamps that drive purely capacitive loads,the buffer stage should not be included,and for this case ,the output stage is clearly not a consideration.

Added after 9 minutes:

Noise is another important consideration when choosing which input stage to use .Perhaps the major noise source of MOS opamps is due to 1/f noise caused by carriers randomly entering and leaving traps introduced by defects near the semicondutor surface.This 1/f noise source can be especilly troublesome unless special circuit design techniques are used.Typically,p-channel transistors have less 1/f noise than n-channel transistors since their majority carriers(holes) have less potential to be trapped in surface states.Thus ,having a first-stage with p-channel inputs minimizes the output noise due to the 1/f noise.The same is not ture when thermal noise is desired.When thermal noise is referred to the input of the opamp ,ti is minimized by using input transistors that have large transconductances ,which unfortunately degrades the slew rate.However ,when thermal noise is a major consideration ,then a more modern architecture,such as a folded-cascode opamp ,is normally used.

In summary ,when using a two-stage opamp,a p-channel input transistor for the first stage is almost always the best choice because it optimizes slew rate ,unity-gain frequency,and minimizes 1/f noise,with the major disadvantage being an increase in wideband thermal noise.

 

[wanily1983]

hi, holddreams
could you explain that p-channel input-pair stage maximizes the slew rate,hope for ur reply.
regards
wanily

 

[flushrat]

Because for a two-stage opamp
The input SR is 2*I(m1)/Cc, where m1 is the input device, Cc is compensation capacitance.
Additionally, the unit-gain bandwidth is gm1/Cc,
With above equations, we get SR=2*I(m1)/Cc=2*I(m1)*wu/gm1=vdsat(m1)*wu, where vdsat(m1)=vgs(m1)-vth
So pmos input-> larger vdsat-> larger SR

 

[tony_wu_ad]

I think it is just noise. PMOS has low noise than NMOS.

But ,if the input voltage level is much large, maybe use both PMOS and NMOS

 

[gszczesz]

All the comments above are fairly valid and I would give it a lot of weighing when designing RF amplifiers...

However, being an IC designer and having worked with RF circuits as well as Power Circuits, the majority of Op-Amps are designed for low frequency biasing/control type applications where 1/f noise is not a consideration. In my experience, 90% of the time the input stage is chosen based on the input signal's voltage range.

If you want a ground sensing amplifier, you put a PMOS front end. By connecting it's body contact to your supply, you create the largest Vt. Since a MOS stays in the saturation region right up to Vds = vdsat, a high Vt allows you to measure the lowest input signal, right down to below -1V levels on a typical process. The same is true if you use an NMOS for >supply level sensing.

What I'm trying to point out is that while someone out there has tried to make an argument for an "ideal" front end, do not read it as gospal. This ideal consideration is for a very particular requirement. Most of the time your circuit requirements will demand an NMOS or PMOS front end based on different factors then what the "ideal" front end was argued for.

 

[montage2000]

COMMON MODE V OR SMALL NOISE

 

[fashion]

There are many benifits using PMOS as input stage,
for example: 1.there is no body effect 2.used in low input voltage 3.its psrr is better than nmos input stage.

 

[puyeng]

There are many benifits using PMOS as input stage,
for example: 1.there is no body effect 2.used in low input voltage 3.its psrr is better than nmos input stage.

how can the psrr is improved with pmos input stage? can you explain it further? thanks

 

[avinash]

the psrr of pmos input pair is higher because it suffers no body effect.correct me if i am wrong.