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In QRC in there are two options for generating SPEF, one is Transistor SPEF, and the other is Cell-level SPEF. You need "Cell level SPEF".
Standard approach in Assura LVS - is to supply all stdcells/macros in ?dspfcells or ?preserveCell.
The following restrictions should be kept in mind when...
check encounter commands - loadLefFile, loadDefFile
Make sure you load tech-lef first (must), then load all cell-lefs - then only load the DEF, make sure all dependencies are loaded.
1. Run TQRC - it will automatically generate mapping between LEF & tech - you can check the log to find where it gets created.
2. You can keep following CCL command option - which can be used in Signoff-QRC run :
extraction_setup \
-technology_auto_layer_map true \
..
Etc.
BTW...
Always RLCK, never RLC.
Now a days PEEC is default, which is accurate.
For skin & proximity effect - use Ladder-network.
In usual GSG [Ground-Signal-Ground] please do include - ground strips in RLCK extraction, they have definite role..
If netlist size is too large - try RLCK reduction, however...
Your understanding is absolutely right.
- substrate extraction will give you fairly accurate Q - that will be very close to some EM solvers.
The issue in my experience I faced with few EM solutions in lower nodes - they do not model erosion, loading-effect, RIE (Reactive Ion Etching) as...
There are more than one ways to do that.
QRC substrate handling methodology has been changed sin 8.x [exact version number I forgot] - there are detailed and good technical reasons backed by many big design house and fab. In new versions of QRC, the back-gate of MOS will get ideal VSS/VDD [based...
Use foundry provided Density rules - as freebird stated above.. these are kind of DRC rules..
Calibre, PVS, Assura can do a density check.
Back to Basics:
Metal Density - is a point function, and therefore various functional representations are possible, {there is nothing like absolute value of...
More VIAs should increase the capacitance.
Perhaps I should also ask - Which technology node you are working with.
Regardless of technology node, in terms of Physics, yes, for a given net - as you increase number of VIAs - they add more metals in the 3D space - therefore more surface area -...
Yes, you can extract all of RLCK [Resistance, Capacitance, Self-Inductance, and Mutual-Inductance] of all interconnect wires[for smaller blocks], or selective nets[for larger designs], by using Cadence QRC extraction tool. Inductance extraction is usually required for for higher frequencies - I...
In the worst case, if you cannot find either IRCX, or ICT, or ITF etc.. you must get the the DRM {Design Rule Manual}, and associated linked documents for the specific foundry/process.
Get as much info as possible - on the metal-stack ::
Metals, dielectrics, passivation, substrate, etc.. with...
This is not an issue. This is to make sure someone does not change the technology during RC extraction.
QRC reads Technology information - from LVS.
I should ask you now : :)
While running LVS - did you select the "Technology" right? - if yes, then QRC run form will inherit that appropriately...
I'd recommend the blackBox LVS - flat QRC-RCX flow.
Everything else would remain same. blackBox the cells - which you want functional/schematic.
To have blackBox working with LVS match, you may need to tweak around your LVS extract.rul to have blackBoxLayers, pinLayer etc.. so that you retain...
You need a Ref_Node, in physics we call that a reference-ground-plane, for the E-fields that gets decoupled to this node.
There are few small , however important things, once understood and taken care of - rest is very easy.
From layout perspective the substrate - is the reference node.
If you...
In the first run - perhaps you had enabled - parasitic resistor models.
This is available on the Netlisting Options tab..
Solution - either keep the model printed as a comment - else - do not enable this.
Check Assura Physical Verification Developers Guide.
Verilog does not explicitly support global signals, but it does support the constant signals of tie0 and tie1. Assura treats them as global nets.
For LVS to connect tie0 and tie1 to your real ground and power nets, you should add the
joinNets...
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