How to generate gate level spef using cadence tool

[question_answer]

Hi All,
I have created a hierarchical layout and hierarchical schematic. On the top level of the layout and schematic, there are just some connection between standard cells. I did Virtuoso LVS and Virtuoso QRC to generate a spef file for static timing analysis. However, when I looked into the spef, it was in transistor level. It seems the extractor did not recognize my layout as several gates, instead, it recognized it as bunch of transistors.
I did try change some setting from LVS. I added ' ?preserveCell ' under avParameter, but nothing changed in the .spef .
Can someone tell me how to generate a gate level spef from a manual place and route layout? Thank you all...

 

[sat]

In QRC in there are two options for generating SPEF, one is Transistor SPEF, and the other is Cell-level SPEF. You need "Cell level SPEF".
Standard approach in Assura LVS - is to supply all stdcells/macros in ?dspfcells or ?preserveCell.

The following restrictions should be kept in mind when specifying the DSPF cells:

* All DSPF cells must have proper power and I/O pins instead of net labels. Even a single missing pin causes the flow to fail. Pin names can be checked from the LVS-runName.erc file in the LVS run directory.

* Pin swapping is not allowed in the DSPF flow.

* Each DSPF cell must be unique. Cell variants are not allowed.

* All DSPF cells are fixed, preserved, and bound. The cannot be expanded to resolve LVS issues.

You must make sure - (check <LVS-runName>.csm) - all cells matched in hierarchy - and *no* cell expansion / flattening / climbing happened.
In the LVS-extracted netlist no device should be present directly at the top.

?dspfCells ( textFile ”mySPFCellsList.txt” )
?preserveCell - will also do the job.

It is also recommended to use ?preserveShapes (to avoid shape climbing) and so on..