does capacitance of the net depend on the no of vias?

[ms_90]

i know that we can reduce the resistance of net by adding more no of vias or contacts

but do these more no of vias will help to reduce the capacitance?

if yes then can someone please explain the concept?

 

[sat]

More VIAs should increase the capacitance.

Perhaps I should also ask - Which technology node you are working with.

Regardless of technology node, in terms of Physics, yes, for a given net - as you increase number of VIAs - they add more metals in the 3D space - therefore more surface area - therefore more capacitance.

[ You may find - capacitance is not increasing even after increasing VIA-count - so please read below]
Now, there are couple of questions ::
- whether the extraction tool is capable to extract VIA caps [Via-to-Via, Via-to-neighbor-metal, Via-to-substrate and so on], sometimes called explicit-via-capacitance modeling.
- Even if the extraction tool is capable to extract such, whether such VIA-cap models are enabled in the first place in the technology file,
- even if both the points above are yes/true, if user is enabling/disabling such via-cap extraction by run-time control.

Regarding technology nodes, older ones like 0.25um, 0.13um and even 90nm nodes - in my experience, majority of foundries has *not* enabled such feature - so you may not see increased capacitance even if you increase number of VIAs, that does not mean - it is not there - it is just the case of accuracy tradeoff. FYI in lower nodes 28nm, yes VIA caps are very much present.

Please note, in above, by VIA I assumed: VIA = metal-to-metal VIA [like V12=M1-to-M2, or, V45=M4-to-M5], not the "contact", which is either metal-to-diffusion, or metal-to-poly, although conceptually they are very similar, for legacy reasons, foundry treated them in a different way. Even at 130nm node some foundry have contact-to-Poly, contact-contact cap modeled, but no modeling for V12-v12 cap, or, V34-V34 cap and so on..