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i am kinda lost in designing control unit for my 32bit ALU .. All i have is 4 modules namely addition,multiplier,logic and shifting. So i need to design a control unit for all these modules so that i can choose any module i want.. but now i came to know i cannot use condition statements to...
i could not get the correct result when i run the program...my aim is when en1 is 1 and module should work and when en2=1 or module should work and so on...
Thanks syedshan...can you explain me with some example?
i tried this program and it is showing wrong results...
module arithmetic(A,B,S,out);
input A,B;
input [1:0] S;
output out;
wire en1,en2,en3,en4;
assign en1=(~S[0])&(~S[1]);
assign en2=(S[0])&(~S[1]);
assign en3=(~S[0])&(S[1]);
assign...
how can i call a module from case or if else statement in verilog?
i need to make a module instantiation whenever particular condition occurs...can someone make me clear on designing control unit like that?
Thanks Gaurav ! that really helped !
I just need a verilog simulation.. i need efficient shifting (right and left) for 32 bits .. Can you give me the code for that ? using binary search ?? We are basically designing high performance 32 bit ALU .. done with multiplier,adder and logic modules...
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