how can we enable and disable the modules in verilog?

[SantoshSoundararajan]

hey guys help me out here...i need u to give me some examples to make a module enabled or disabled whenever we need in verilog HDL....

 

[TrickyDicky]

you already had some in your previous post.

 

[SantoshSoundararajan]

yeah not able to understand it...im stuck with that...

 

[TrickyDicky]

I suggest going back to the origional thread. There was a hint given to you - you wired 4 outputs together, so they clash. Perhaps you need to google about how to build a mux.

 

[mrflibble]

So unstuck yourself by trying some more. As for enable/disable ... and also looking at the other thread ... you can only do that at SYNTHESIS time, not at run time. Assuming we are talking hardware here, not just simulation.

So assuming real hardware ... you can use a parameter in your higher level module to decide to instantiate or not. And then you use for example an initial block or generate or even `ifdef.

Anyways, if you are pro-active about your help I have now given you a couple of google terms. "conditional synthesis verilog parameter initial"

And just to see if that initial google query would work:

**broken link removed**

There's some inspiration you can use to solve your problem.