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Recent content by sam31

  1. S

    OVM SystemVerilog cookbook from Cadence

    Re: need ovm_svcb.pdf Only cadence customer to sourcelink
  2. S

    What's the best VHDL/Verilog/SystemVerilog editor?

    editra systemverilog Best one is DVT eclipse plug in
  3. S

    Problem with inserting scan and DFFs

    Re: insert scan problem Hi, I think funzero method is best for scan insertion DC provides all commands to do this when you use compile -scan command DC instantiate SDFF and put scan_in & test_se of all SDFF to '0' then with insert_dft command DC make the scan data path according to scan...
  4. S

    Differences between SPEF and SDF which are used in static timing analysis

    .spef file Hi, You can also use the SPEF to generate a SDF (with Primetime) and then use this SDF for post layout simulation
  5. S

    how to build integrated clock gating cell ?

    integrated clock gate You need a dedicated cell for gating clock in your design lib These cells are designed for this task
  6. S

    problem with two clocks

    1-create_clock for each clock 2-set_fix_hold [all_clock] 3-set_propagated_clock (not need if no clock tree) 4-set_input_delay and set_output_delay for synchronous signal related to one clock domain
  7. S

    [help] how to set_dont_use in soc encounter?

    encounter autoctsrootpin Hi, Why you don't want to use buf8 ,buf12 and so on ?
  8. S

    ATPG and post-layout simulation

    Hi, There is timing violation?
  9. S

    Bus synchronization when transferring data from one clock domain to another domain

    Re: bus synchronization Hi, Generally I use FIFO with two port for each clock domain ask me if you need help Best regards
  10. S

    Is formal verification really required?

    Yes !!!! Why? Formal verification tool help us to find bad RTL code that induce bad synth result earlier in design cycle >> save design time + cost + you don't need post synthesis/layout simulation if you make RTL simulation + formal verification RTL vs synthesis/layout + STA
  11. S

    synthesis question on FSM, error on syntheis netlist!!

    Hi, I agre check your RTL code first! I think that you must rewrite your code and before read some application notes on FSM coding
  12. S

    Realizing full adder from MUX (2:1)

    mux to adder :idea: For SUM Mux controlled by A, B mux input 0 connected to Cin mux input 1 connected to Cin inverted mux input 2 connected to Cin inverted mux input 3 connected to Cin For CARRY Mux controlled by A, B mux input 0 connected to '0' mux input 1 connected to Cin mux input 2...
  13. S

    how to perform matrix operation in vhdl?

    matrix vhdl Hi, VHDL is a hardware programming langage You can make your own lib with function/procedure to compute matrix like any other programmation langage (ADA, C ....) ! Why you want use VHDL for matrix operation? There is some software like Matlab that have all features for this task
  14. S

    Help me to design a NOR gate using THREE tri-state inverters

    Re: NOR gate Design :idea: : I consider a :arrow: tristate input x :arrow: tristate output e :arrow: tristate enable (active high) gate U1, U2 and U3 U1(a) connected to '0' U1(e) connected to first input U1(x) connected to U3(e) + pullup U2(a) connected to '0' U2(e) connected to second...
  15. S

    what's SPEF and what information does it contains?

    star-rcxt spef d_net SPEF : parasistic parameter R (ohm) & C (farad) for RC timing modeling Used after layout to back-annotate timing for STA & simulation
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