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It probably isn't important at the design stage you've mentioned. But, I think formal verification is very useful when a post-layout netlist edit needs to be made. As you probably know, a post-layout netlist is when all gates have been positioned on the die and connecting wires have been routed.
For instance, a case can happen when a bug is found late in the design cycle and it has been determined that it would be too costly in schedule and labor to relayout the chip. So, typically, an approach to fix this problem would be to make a change in RTL to fix the bug and run simulation to verify the fix. Once that is complete, hopefully the fix is a minor one, edit the netlist and compare RTL with the netlist via formal verification.
Yes !!!!
Why?
Formal verification tool help us to find bad RTL code that induce bad synth result earlier in design cycle >> save design time + cost
+ you don't need post synthesis/layout simulation if you make RTL simulation + formal verification RTL vs synthesis/layout + STA
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