problem with two clocks

[vahid_roostaie]

Hi!

I have to seperated asynchronous clocks in my design.both of them are input ports
that have their own registers in my design.I used approperiate synchronizers and the other needed techniques in clock boundary and have no problem in design.

but my problem is defining and using DC commands for these two clocks.

how can I use the following commands for two clocks?do I have to repeat each of them for each one of my clock?

1-create_clock.
2-set_fix_hold.
3-set_propagated_clock.
4-set_input_delay and set_output_delay.

how can I insert clock gating in my design for two seperated clocks.I used set_clock_gating_style but this command is not related to clock.is there any other way to do this?

thanks alot

 

[leeenghan]

Hi vahid_roostaie,

You will need two create_clock.

Don't fix hold in front-end unless you are doing 0.35um or larger technology. Fix hold in layout after clock tree is inserted.

You need set input and output delay. If a pin can be driven by both clocks then you need to specified for each clock.

I think clock gating insertion is independant of how many clock you have.

Regards,
Eng Han

 

[utmseng]

if 2 clocks are asyn, why can't we set them to false path?

 

[archillios]

hi utmseng,
I think we can set the paths to false if 2 clocks are asyn,and we use properly synchronizers between them.

 

[sam31]

1-create_clock for each clock
2-set_fix_hold [all_clock]
3-set_propagated_clock (not need if no clock tree)
4-set_input_delay and set_output_delay for synchronous signal related to one clock domain