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Hi,
You need to check following points b4 chose any FPGA.
1. How much is the frame size?
2. What is the resolution has been targeted?
3. How much BRAM in the FPGA to process frames? --> Though you are using external memories like DDR/SRAm/Flash etc.
You atleast need 2-3 frames to be stored...
Lower LSBs of 1st module can be connect to LSBs of the 2nd module.
You can connect at top level module as per the following -
out(36:28) => E(8:0);
out(27:19) => C(8:0);
out(18:10) => B(8:0);
out(9:0) => A(8:0);
Hope this helps.
~Sachin
You need to add unsigned library for using signed/unsigned numbers to be used in your code.
Also try to use '(' brackets to complete any expression bonding.
~Sachin
Hi,
- First check how complex is your design.
- Then try to check if this complexity are ready to use .. i mean any IP which can be easily implemented available freely with FPGA vendors.
- What will be you maximum frequency targeted?
- check how much IO would be required and their standard?
-...
setup hold time clock to out fpga
Hold is at highest priority then Setup. FPGA can not perform or fails to operate if HOLD violations remains in the design.
The Setup violations directly gives the best operating frequency of the FPGA (performance).
Setup violations are broadly classifies based...
Re: Depth of FIFO
hi guys,
here is the link where from subramaniam copied and paste the reply.
https://www.asic-world.com/tidbits/fifo_depth.html
Subraman - please try to post the answer by ur explanation otherwise provide direct link if u have any.
hi
Ya both are easy & simple.
If you are familiar with C coding then go for verilog, otherwise VHDL.
As of my experience you can start with VHDL.
regards,
Sachin
Re: ISP programming of PROM in slave serial mode. is it poss
There are 3 classical ways to configure your FPGA:
1) You use a cable from your PC to the FPGA, and run a software on your PC to send data through the cable.
2) You use a microcontroller on your board, with an adequate firmware to...
vhdl help
Hi Balakrishna,
Plz put a if condition like,
if count = 0 then
pulse <= '1';
else
pulse <= '0';
end if;
This condition should be under the clock, which you are going to use. With this condition your pulse would be equal to one clock duration for high.
Please try this and let...
Hi ahmedagha,
For your 1st query, I would say 'No' for PP-III connection, you did not worry about INIT pin for Slave serial connection. But this INIT pin of FPGA must be connected to processor or controller which ever you are going to use. See datasheet of Spartan for this connections. (see...
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