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When two wire segment are in close proximity, they interact with each other electrically, this is an account of coupling capacitor between these two nets. This phenomenon is called crosstalk.
or you can say, victim net gets affected by aggressor net.
To avoid cross talk, you can insert buffer...
Hi kapil_vlsi1,
Can you explain these some of region properties like hard_region, member_hard, nonmember_hard, member_route_fence, nonmember_route_fence etc.
thanks.
Hello all,
For what purpose regions have been created during floorplan? What are the advantages of regions? How can we assign cells to particular regions and which cells? how to decide that?
Thank you.
sorry, its not .itc, its .ict..
Actually i got to know about elcap..i also tried to generate .ptf file from .ict file using info given in olympus user manual. But not suceeded..
Have you done such experiments of converting .itc or .itf or .nxtgrd, or .ircx or .conf file format to .ptf file format?
Thanx pavanks..
I have another query that when i saw my timing report, i found that there are 3 buffers placed in common clock path but delay corresponding to launch path and capture path was different..
How that is possible? In launch path, delay till these 3 buffer is 356ps and for same...
Thanx rca,
actually i gone through theory, so i find that three way of cell row configuration:
1) flip every other cell row which does not leave a gap between the cell rows.
2) flip every other cell row, but leave a gap between every two cell rows.
3) leave a gap between every cell row, and...
Thanx rca,
Can you explain 2?
height of gap between cell row is minimum pitch distance of metal1 in case of when we flipping cell row, is this right? or it may vary depending on design requirement?
And under what circumstance, we not go for flipping cell row and why we go for flipping cell...
Hello all,
Discuss here the design challenges of clock tree synthesis.
CTS quality checks: skew, minimum pulse width, duty cycle, latency, slew, clock tree power, signal integrity and cross-talk.
From these checks, which check we have to give more priority?
Can anyone arrange these term acc...
Hello all,
I wanted to clear some basic doubts.
1) What is the reason for flipping the cell rows?
2) When you need to leave a gap in between the cell rows, how do you
determine the height of the gap?
3) If you are to use both vertical and horizontal stripes, what are the
considerations to...
standard cell height in technology node 45nm => 1.4um
You can refer this to know better
https://usebackend.wordpress.com/2012/10/25/asic-physical-deisgn-for-stdcells/
Thanx for reply pavanK.
As you know, insertion delay is the time taken for the signal to propagate from the clock root pin to leaf clk pin.
And insertion delay directly proportion to clock tree levels, am i right?
In that case if i increase insertion delay then clock tree levels are increase...
Thank you guys..really nice explaination.
Hello pavanks,
you mean to say that single buffer delay is not exactly two inverter delay, am i right?
And can you tell me that how inverters help in improving, i mean achieving good skew and better pulse width? As buffer itself also contains two...
Common clock path in Clock tree synthesis (CTS)
Hello all,
is there any command in ICC or Olympus-SOC to control buffers added to common clock path (of launch clock path and capture clock path) during CTS(clock tree synthesis)
Thank you.
OR any other way to control buffer insertion in...
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