CTS design challenges

[ramesh28]

Hello all,

Discuss here the design challenges of clock tree synthesis.
CTS quality checks: skew, minimum pulse width, duty cycle, latency, slew, clock tree power, signal integrity and cross-talk.

From these checks, which check we have to give more priority?
Can anyone arrange these term acc. to priority in ascending order considering various design aspects like timing, power, area etc?
And explain why we go particular checks ahead of others?

Thank you..

 

[pavanks]

We need to achieve all of these together.
Only power might be a issue in low power.
Apart from that all the others r required.

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