Some question on floorplanning and cts

[ramesh28]

Hello all,

I wanted to clear some basic doubts.
1) What is the reason for flipping the cell rows?
2) When you need to leave a gap in between the cell rows, how do you
determine the height of the gap?
3) If you are to use both vertical and horizontal stripes, what are the
considerations to decide which one should be added to the power
plan first?
4) The strategy to synthesize the clock tree is highly dependent on the
features of the P&R tool you are using. As a P&R engineers, how do
you find out all the requirements of the clock tree?

reply..

Thank you

 

[rca]

1) some std cell are design with the power pins along the border, which means without flipping the row, you need a space between ground and supply pins of the std cell.
2) you add the gap to respect different NWell implementation for example.
3) I think the lower layer in first. if you place the highest layer in first, the stack via, will block the opposit stripe power net.
4) documentation and suer info in Cadence forum for example.

 

[ramesh28]

Thanx rca,

Can you explain 2?
height of gap between cell row is minimum pitch distance of metal1 in case of when we flipping cell row, is this right? or it may vary depending on design requirement?

And under what circumstance, we not go for flipping cell row and why we go for flipping cell row? is that depend on number of metal layers availabe for routing?

 

[rca]

2) in case of different nwell pockets

in case of flipping row, normaly no gap is required.
I never made (since 12years) without flipping row.

 

[ramesh28]

Thanx rca,

actually i gone through theory, so i find that three way of cell row configuration:
1) flip every other cell row which does not leave a gap between the cell rows.
2) flip every other cell row, but leave a gap between every two cell rows.
3) leave a gap between every cell row, and not flip the cell rows.

The purpose of the gaps is to allocate more resources for the inter-connect routings.

Thats why i eagerly wanted to know about non-flip cell row configuration. I think due to number of metal layers available for routing nowadays in asic, we are not using this configuration, am i right?

 

[rca]

Right, with 3 or more metal layers you do not need space between rows.
After it is really std cell dependant, how there are made, how many layers the std cell itselfs used.