Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

pulkit.vlsi

Recent content by pulkit.vlsi

P
Implement carrier detection logic in FPGA

78Q8392L.
- pulkit.vlsi
- Post #5
- Dec 26, 2022
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
Implement carrier detection logic in FPGA

FPGA will deal with digital part only. One side it is connected to MAC. other side it is connected to transformer which is further connected to a 10 base 2 transiver IC.
- pulkit.vlsi
- Post #3
- Dec 26, 2022
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
Implement carrier detection logic in FPGA

Hi, I am working on an application where i need to implement carrier sense logic for and half duplex 10Base2 interface. in one ieee document i got below detail: Please help me understand this logic.
- pulkit.vlsi
- Thread
- Dec 26, 2022
- Replies: 5
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
VHDL code for I2C master write/read

Thanks for your reply TrickyDicky. Here is my I2C master code. I am writing "11110000" on "00000001"th location in eprom. but when i go to read this location, i am getting only "11111111". Can you have a look n help me to find mistake in this code. Thanks...
- pulkit.vlsi
- Post #3
- Mar 13, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
VHDL code for I2C master write/read

Can anyone help me to write a simple working vhdl code for I2C master write and read interface with FPGA ? I am doing this project for interfacing AT24C01A eprom with FPGA. Thanks in advance.
- pulkit.vlsi
- Thread
- Mar 12, 2014
- Replies: 4
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
vhdl:packages: procedure calling

can i call a procedure in an another procedure ?
- pulkit.vlsi
- Thread
- Nov 26, 2013
- Replies: 1
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
interleaver & deinterleaver in digital communication

can anybody guide me to get the basics of interleaver & deinterleaver, used in digital communication. Thanks in advance.
- pulkit.vlsi
- Thread
- Dec 26, 2012
- Replies: 3
- Forum: Digital communication
P
Using shift operator in VHDL code

hi, I am using left shift operator in my vhdl code, but it is showing error. are these operators synthesizable ? can anyone help me with a vhdl code using shift operators thanks in advance
- pulkit.vlsi
- Thread
- Aug 7, 2012
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
simple vhdl code for I2C master

Hi I am trying to make a simple vhdl code for I2C master, but my code is not working. Can anyone help me regarding this matter?. Thanks in advance
- pulkit.vlsi
- Thread
- Jul 19, 2012
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
using FIFO for two clock domain

hello, I ma doing a project in which i have to transfer data between two domains. But the problem is that, these domains working on two different clocks. clock1 > clock2. to solve this problem i will have to use a FIFO between these domains. But i am not aware of FIFOs. i dont know how a FIFO...
- pulkit.vlsi
- Thread
- Jul 6, 2012
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
flip fliop conversions

how can we design a T flip flop using a JK flip flop?
- pulkit.vlsi
- Thread
- Jun 28, 2012
- Replies: 1
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
[SOLVED] flip flops design using latchs

how can we design a flip flop using latch ?
- pulkit.vlsi
- Thread
- Jun 28, 2012
- Replies: 22
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
can a latch have a clock

thankx all for the reply :)
- pulkit.vlsi
- Post #6
- Jun 15, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
can a latch have a clock

can a latch have a clock ?
- pulkit.vlsi
- Thread
- Jun 13, 2012
- Replies: 5
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
P
[SOLVED] std_logic values in vhdl

Thanks everyone for the reply.... :)
- pulkit.vlsi
- Post #8
- Jun 13, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

pulkit.vlsi

Welcome to EDAboard.com

Recent content by pulkit.vlsi

Implement carrier detection logic in FPGA

Implement carrier detection logic in FPGA

Implement carrier detection logic in FPGA

VHDL code for I2C master write/read

VHDL code for I2C master write/read

vhdl:packages: procedure calling

interleaver & deinterleaver in digital communication

Using shift operator in VHDL code

simple vhdl code for I2C master

using FIFO for two clock domain

flip fliop conversions

[SOLVED] flip flops design using latchs

can a latch have a clock

can a latch have a clock

[SOLVED] std_logic values in vhdl

Part and Inventory Search

Connect with us

Online statistics

Forum statistics