Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

vhdl:packages: procedure calling

Thread starter pulkit.vlsi
Start date Nov 26, 2013

Status: Not open for further replies.

Nov 26, 2013

#1

P

pulkit.vlsi

Junior Member level 1

Junior Member level 1

can i call a procedure in an another procedure ?

Nov 26, 2013

#2

T

TrickyDicky

Advanced Member level 7

Advanced Member level 7

Yes you can.

Status: Not open for further replies.

Similar threads

R
[SOLVED] VHDL code "skip" a line in write procedure
- Started by Raeiu
- Jan 19, 2024
- Replies: 8
PLD, SPLD, GAL, CPLD, FPGA Design
C
Problem calling a function from my vhdl project in Vivado.
- Started by Cesar0182
- Oct 7, 2019
- Replies: 4
PLD, SPLD, GAL, CPLD, FPGA Design
M
Calling VHDL code in Verilog Code
- Started by manjunath_crl
- Sep 7, 2018
- Replies: 4
PLD, SPLD, GAL, CPLD, FPGA Design
S
Facing difficulty in executing the code for calling function using tri-state buffer
- Started by snehan
- Nov 8, 2018
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
K
procedure of PROCESS in VHDL
- Started by kahroba92
- Jul 26, 2018
- Replies: 22
PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top