using FIFO for two clock domain

[pulkit.vlsi]

hello,

I ma doing a project in which i have to transfer data between two domains. But the problem is that, these domains working on two different clocks. clock1 > clock2.

to solve this problem i will have to use a FIFO between these domains. But i am not aware of FIFOs. i dont know how a FIFO works.

Can anyone guide me about FIFOs of suggest me any link for the complete tutorials about FIFO

Thanks in advance

 

[TrickyDicky]

The manufacturers all provide FIFO IP blocks that you can use in your own designs so you dont have to build your own.

altera: https://www.altera.com/literature/ug/ug_fifo.pdf
xilinx : https://www.xilinx.com/support/documentation/ipmeminterfacestorelement_fifo_fifogenerator.htm

Essentially a FIFO (First In First Out) is a dual port ram with a counter on the read and write ports as the address. The difference between the two counters will tell you how full it is. With dual clocks you have to be careful how you transfer the address over the clock domains, so many of them use grey counters.

Make sure your Data rates match in both clock domains. FIFOs are good at handling bursty data and transfering data over clock domains but if you have a data rate imbalance you will fill the FIFO up and jam up your system.

 

[TonyM]

hello,

I ma doing a project in which i have to transfer data between two domains. But the problem is that, these domains working on two different clocks. clock1 > clock2.

Do you have to transfer any control/status signals as well or just data? That's quite different. That's ignoring the FIFO control/status signals.

And is your data wider than a single FIFO can be in your FPGA? (I'd guess that your FIFOs are 36 bits wide max.)