Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi
In general speaking latch does not have any clock ant its output depends on its input for example we have SR latch witch is stable when both inputs are low and change when SR = 01 or 10 but if we add clock to latch it changesto Flip flop which can have edge triggered or level triggered clock
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.