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Recent content by omar-malek

  1. O

    ASK modulation and data slicer in UHF band

    Hi every body Any one know project about ASK modulation and demodulation or data slicer i want used it in design of UHF RFID reader
  2. O

    i serach the lowest power MCU

    Hi to all Any body know the lowest power Microcontroller? Thank you
  3. O

    Power Result of DC Cell Leakage Power more than Total Dynamic Power is normal ????

    i have get this resulte after synthesis Cell Leakage Power more than Total Dynamic Power , is that normal Cell Internal Power = 19.8773 nW (23%) Net Switching Power = 65.3011 nW (77%) --------- Total Dynamic Power = 85.1783 nW (100%) Cell Leakage...
  4. O

    VHDl equivalent of : assign signal1 = (signal2<= signal3);

    hi to all can any one give me the equivalent in VHDL of this verilog assign signal1 = (signal2<= signal3);
  5. O

    how i know power cosumption after synthesis using DC

    Hi to all i have power report after synthesis using synopsys design compiler and there is many power type Cell internal power = Net switching power = Total dynamic power = cell leakage power = so i need what power my design consume Thank you.
  6. O

    power optimisation : Top-down design vs. Bottom-up design

    hi to all, for power optimization what is the better method to syntheses the design Top-down design or Bottom-up design?? thank you
  7. O

    Problem with en signal of speed clockand enable signal with slow clock

    Hi to all, i develop a system using VHDL language. so i have to module one work with speed clock and generate signal enable for one cycle speed clock, this signal wired to other enable signal that work with slow clock, so the problem the enable signal of second system (work with slow clock)...
  8. O

    What is the diffrenece between timining analysis for FPGA and ASIC

    What is the diffrenece between timining analysis for FPGA and ASIC so an engineer of digital design choice between timing analysis of fpga and asic . the same for the constraint.? thank you
  9. O

    The different between Leonardo (Mentor Graphics) a Design Compiler (Synopsys)?

    hi to all i want to know the different between Leonardo (Mentor Graphics), Design Compiler (Synopsys) and if i can use design kit of 32 nm of synopsys or 65 nm of st microelectronic for asic synthesis?
  10. O

    question about : conv_std_logic_vector

    so i will explain where i used this function in my design i receive a frame folowing a standard my frame is 16 bits, so to detect this frame i use a counter this counter count the number of receive bits and this received bit has a value like 11110000110 .
  11. O

    question about : conv_std_logic_vector

    but i wan to know the signification of conv_std_logic_vector(13, 8) ; 13? 8?
  12. O

    question about : conv_std_logic_vector

    hi to all is this correct to vhdl: can any one explain me : Data_reg = conv_std_logic_vector(13, 8) with: Data_reg = conv_std_logic_vector(13, 8) ; thanks
  13. O

    Explain vhdl ligne " conv_std_logic_vector(CONV_INTEGER(cnt)"

    hi to all . Can any one explain me this ligne in the code of counter cnt <= conv_std_logic_vector(CONV_INTEGER(cnt) + 1, width); thank you. ibrary IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity COUNTERCLR is generic ( width ...
  14. O

    Equivalent vhdl of this verilog

    i begin to convert this vhdl code to verilog can any one help me to finish the conversion? Verilog code: module rfid_reader_tx ( // basic setup connections reset, clk, reader_modulation, // control signals...
  15. O

    equivalent of vhdl for this verilog

    thank you i want this equivalent please thank you in advance: current_bit <= tx_packet_data[current_tx_bit]; bit_transition <= data1_bit_transition | (not current_bit & data0_bit_transition); bit_end <= data1_bit_end nor (!current_bit & data0_bit_end); and what is...
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