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Equivalent vhdl of this verilog

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omar-malek

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i begin to convert this vhdl code to verilog
can any one help me to finish the conversion?

Verilog code:
module rfid_reader_tx (
// basic setup connections
reset, clk, reader_modulation,
// control signals
tx_done, tx_running, tx_go, send_trcal,
// timing information
delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts,
// payload information
tx_packet_length, tx_packet_data
);

input reset, clk, send_trcal, tx_go;
output reader_modulation;
output tx_done, tx_running;

input [15:0] delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts;

input [6:0] tx_packet_length;
input [127:0] tx_packet_data;

reg [2:0] tx_state;
parameter STATE_IDLE = 3'd0;
parameter STATE_DELIM = 3'd2;
parameter STATE_DATA0 = 3'd3;
parameter STATE_RTCAL = 3'd4;
parameter STATE_TRCAL = 3'd5;
parameter STATE_DATA = 3'd6;
parameter STATE_WAIT_FOR_RX = 3'd7;

reg modout;
assign reader_modulation = modout;

reg [15:0] count;
reg [6:0] current_tx_bit;

reg tx_done, tx_running;

wire current_bit, data0_bit_end, data0_bit_transition, data1_bit_end, data1_bit_transition, bit_transition, bit_end;
wire [15:0] data0_end_count, data1_end_count, data0_tran_count, data1_tran_count;
assign current_bit = tx_packet_data[current_tx_bit];
assign data0_end_count = tari_counts+pw_counts;
assign data1_end_count = tari_counts+tari_counts+pw_counts;
assign data0_tran_count = tari_counts;
assign data1_tran_count = tari_counts+tari_counts;
assign data0_bit_end = (count >= data0_end_count);
assign data0_bit_transition = (count >= data0_tran_count);
assign data1_bit_end = (count >= data1_end_count);
assign data1_bit_transition = (count >= data1_tran_count);
assign bit_transition = data1_bit_transition | (!current_bit & data0_bit_transition);
assign bit_end = data1_bit_end | (!current_bit & data0_bit_end);

wire rtcal_end, rtcal_transition, trcal_end, trcal_transition;
wire [15:0] rtcal_end_count, trcal_end_count;

assign rtcal_end_count = rtcal_counts+pw_counts;
assign trcal_end_count = trcal_counts+pw_counts;
assign rtcal_end = (count >= rtcal_end_count);
assign rtcal_transition = (count >= rtcal_counts);
assign trcal_end = (count >= trcal_end_count);
assign trcal_transition = (count >= trcal_counts);



equivalent vhdl


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity reader_tx is
port(
reset, clk, send_trcal, tx_go: in std_logic;
reader_modulation: out std_logic;
tx_done, tx_running: out std_logic;

delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts : in std_logic_vector (15 downto 0);

tx_packet_length : in std_logic_vector (6 downto 0);
tx_packet_data: in std_logic_vector (127 downto 0));
end reader_tx;



architecture Behavioral of reader_tx is

signal STATE_WAIT_FOR_RX : std_logic_vector(2 downto 0);
signal modout : std_logic_vector;
constant STATE_IDLE : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELIM : std_logic_vector(3 downto 0) := "0001";
constant STATE_DATA0 : std_logic_vector(3 downto 0) := "0010";
constant STATE_RTCAL : std_logic_vector(3 downto 0) := "0011";
constant STATE_TRCAL : std_logic_vector(3 downto 0) := "0100";
constant STATE_DATA : std_logic_vector(3 downto 0) := "0101";
constant STATE_WAIT_FOR_RX : std_logic_vector(3 downto 0) := "0110";



signal count : std_logic_vector(15 downto 0);
signal current_tx_bit : std_logic_vector(6 downto 0);


-- reg tx_done, tx_running ;

signal current_bit, data0_bit_end, data0_bit_transition, data1_bit_end, data1_bit_transition, bit_transition, bit_end,
data0_end_count, data1_end_count, data0_tran_count, data1_tran_count :std_logic_vector(15 downto 0);

current_bit <= tx_packet_data[current_tx_bit];
data0_end_count <= tari_counts+pw_counts;
data1_end_count <= tari_counts+tari_counts+pw_counts;
data0_tran_count <= tari_counts;
data1_tran_count <= tari_counts+tari_counts;

data0_bit_end <= '1' when (count >= data0_end_count) else '0';
data0_bit_transition <= '1' when (count >= data0_end_count) else '0';
data1_bit_end <= '1' when (count >= data0_end_count) else '0';
data1_bit_transition <= '1' when (count >= data0_end_count) else '0';

bit_transition <= data1_bit_transition | (not current_bit & data0_bit_transition);
bit_end <= data1_bit_end nor (!current_bit & data0_bit_end);

signal rtcal_end, rtcal_transition, trcal_end, trcal_transition;
signal rtcal_end_count, trcal_end_count: std_logic_vector(15 downto 0);

rtcal_end_count <= rtcal_counts+pw_counts;
 

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