VHDl equivalent of : assign signal1 = (signal2<= signal3);

[omar-malek]

hi to all

can any one give me the equivalent in VHDL of this verilog


assign signal1 = (signal2<= signal3);

 

[TrickyDicky]

if signal1 is a boolean:

signal1 <= (signal2 <= signal3);

or for std_logic;

signal1 <= '1' when (signal2 <= signal3) else '0';

 

[permute]

really, signal2 and signal3 should be cast to unsigned. Verilog treats "0100" > "011" while VHDL treats "0100" < "011" for std_logic_vector.

 

[ads-ee]

really, signal2 and signal3 should be cast to unsigned. Verilog treats "0100" > "011" while VHDL treats "0100" < "011" for std_logic_vector.

Verilog would treat "0100" > "011" as 4'b0100 > 4'b0011, while VHDL would error out and complain about mismatched std_logic_vector widths if I'm not mistaken.

 

[permute]

"<" for vectors in VHDL does:

if x'length < y'length then
  z := false;
end if;
for idx in y'range loop -- please assume indexes have been normalized to the standard 0 to N-1
  if x(idx) /= y(idx) then
    if x(idx) < y(idx) then
      return true;
    else
      return false;
    end if;
  end if;
end loop
return z;

Which is pseudocode, but should show the basic way VHDL compares vectors. This method makes the most sense for strings. It is a bit dangerous because it does end up practically being an unsigned comparison when the vectors are the same length. On the other hand, "=" will issue a warning if arguments are unequal length for std_logic_vector. "=" will return false in this case. If you declare these as signed/unsigned (or use ieee.std_logic_unsigned.all) you end up doing all comparisons in the numeric sense. For designs that make heavy use of generics, this can be an issue as any incorrect comparisons are now valid logic instead of warnings (for "=").