question about : conv_std_logic_vector

[omar-malek]

hi to all
is this correct to vhdl:
can any one explain me :

Data_reg = conv_std_logic_vector(13, 8)

with:

Data_reg = conv_std_logic_vector(13, 8) ;

thanks

 

[shaiko]

neither is correct.
It should be:

Data_reg <= conv_std_logic_vector(13, 8) ;

But it's advisible to use the NUMERIC_STD package instead of the STD_LOGIC_UNSIGNED package.
Define your vectors as type unsigned ( or signed ) and use the "to_unsigned" function instead of conv_std_logic_vector.

 

[omar-malek]

but i wan to know the signification of
conv_std_logic_vector(13, 8) ; 13? 8?

 

[imbichie]

Hi omer-malek,

Look at the link, which should help you..

The conv_std_logic_vector function

 

[imbichie]

Hi omer-malek,

Look at the link, which should help you..

The conv_std_logic_vector function

 

[TrickyDicky]

conv_std_logic_vector is not a standard VHDL function. you should use to_unsigned or to_signed from numeric_std instead.

slv <= std_logic_vector( to_unsigned(10, 8) );

 

[shaiko]

TrickyDicky,

You say:
"conv_std_logic_vector is not a standard VHDL function"
Is std_logic_vector a standart type ?
If not, is there a reason to use it besides compatibility with other designs ?

 

[lucbra]

Refer to the std_logic_1164 package.
std_logic_vector is defined as:
TYPE std_logic_vector IS ARRAY (NATURAL RANGE <>) OF std_logic;

Is it a standard type then? I guess not because it is derived of std_logic (which is a subtype of std_ulogic), but everyone will say it is, as it is defined in std_logic_1164.

 

[std_match]

TrickyDicky,

You say:
"conv_std_logic_vector is not a standard VHDL function"
Is std_logic_vector a standart type ?
If not, is there a reason to use it besides compatibility with other designs ?

conv_std_logic_vector is defined in std_logic_arith, which we want to avoid.
std_logic_vector is defined in std_logic_1164, which we want to use.

 

[K-J]

TrickyDicky,

You say:
"conv_std_logic_vector is not a standard VHDL function"
Is std_logic_vector a standart type ?
If not, is there a reason to use it besides compatibility with other designs ?

Generally speaking, when people say something is or isn't a standard in VHDL, what they mean that it is or isn't released in the IEEE standard. std_logic_vector is part of the IEEE standard so it is considered a 'standard', whereas conv_std_logic_vector is not part of the IEEE standard so is not considered a 'standard'. As pointed out, the function 'to_unsigned' will do what 'conv_std_logic_vector' is trying to accomplish, 'to_unsigned' is part of the IEEE standard.

Kevin Jennings

 

[omar-malek]

so i will explain where i used this function
in my design i receive a frame folowing a standard my frame is 16 bits, so to detect this frame i use a counter this counter count the number of receive bits
and this received bit has a value like 11110000110 .

 

[TrickyDicky]

you can still do that with the numeric_std package.