equivalent of vhdl for this verilog

[omar-malek]

Hi to all

i cant find the equivalent of vhdl for this verilog



assign data0_bit_end <= (count >= data0_end_count);

data0_bit_end and count is vector of 16 bits.
thanks

 

[permute]

data0_bit_end <= '1' when (count >= data0_end_count) else '0';

vhdl will also force you to have the correct types. The systhesis tools should correctly report size errors, but I wouldn't rely on it.

this means you might need to import ieee.numeric_std.all, and then cast count/data0_end_count to unsigned -- unsigned (count) >= unsigned(data0_end_count).

 

[omar-malek]

thank you
i want this equivalent please thank you in advance:

current_bit <= tx_packet_data[current_tx_bit];

bit_transition <= data1_bit_transition | (not current_bit & data0_bit_transition);
bit_end <= data1_bit_end nor (!current_bit & data0_bit_end);

and what is the equivalent of reg
and the different between reg and wire