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Recent content by noureddine-as

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    How to apply automatic clock gating partially

    Thanks for the answer. The gating report shows that only a few 1-bit and 2-bit signals haven't been gated because of bitwidth being < 3. Some other registers haven't been gated because they're always enabled. Overall it's about 98% gating. That's okay I guess? For now, there is 1 operation...
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    How to apply automatic clock gating partially

    I'm synthesizing an IP for ASIC, using Design Compiler. When using automatic clock-gating (with the compile command), the post-synthesis functional tests seem to pass for all the sub-modules, except for one which doesn't compute correctly (I still didn't find what exactly is the problem, but...
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    [SOLVED] max_leakage_power violation when using Compile Ultra in Design Compiler

    Okay, thanks for your answers @oratie @ThisIsNotSam !
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    [SOLVED] Typical input/output delay values

    Indeed it's a Floating-Point Unit, and it's a research project and I don't have ideas about the orders of magnitude usually used in industry, that's why I asked the question in the first place. From the answers, it seems that it depends on where it will be used, so for a simple comparison, I'll...
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    [SOLVED] max_leakage_power violation when using Compile Ultra in Design Compiler

    Hi, I'm synthesizing an RTL block using Design Compiler, for an ASIC target. After analyzing and elaborating the design, then specifying some parameters (clock, input/output delays, operating conditions, wire model, ...) I perform compilation. Usually I use this one: compile -exact_map...
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    [SOLVED] Typical input/output delay values

    Thanks for your answer. I'm not sure I understood what you said, I know how to set input/output delays, but how to configure the other ones?
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    [SOLVED] Typical input/output delay values

    Hi, I'm performing ASIC synthesis, for a SystemVerilog IP, while I have a specification for the Minimum Frequency that should be supported, but I have no idea about what could be a typical input/output delay value, what are the values that are usually used in industry ? For now I use 20% of...
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    [SOLVED] SDF file backannotation problem: "Instance X does not have a generic named Y"

    Re: SDF file backannotation problem: "Instance X does not have a generic named Y" Using Verilog behavioural libraries (instead of VITAL VHDL stuff) along with Verilog output Netlist resolves the problem.
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    How to compile VCS simulator (simv) statically? and how to increase performance?

    Hi, I migrated recenly from ModelSim to VCS for performance issues (ModelSim was sooo slow for gate-level simulation plus I always had to generate VCD or FSDB and then feed that to PrimeTime which takes a lot of time and disk space, wheras VCS directly generates the SAIF files I want). The...
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    [SOLVED] How to trace the original of netlist gates back to the original RTL description

    No, what I mean is that, In the IP (which is actually a floating-point unit) there are a lot of arithmetic stuff .. and it's all combinational. So when it's synthesized you no longer no what comes from where .. so I want design compiler to label the names of the cells instances somehow, sow I...
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    [SOLVED] Looking for Synopsys documentation on their outputs formats used in PrimeTimePX

    In addition to what kungchuking and ThisIsNotSam said, you can export the power waveform as FSDB, and then open it using Verdi. There is an option to export in CSV format. I did that a long time ago, but I figured out that the CSV file is just so huge that I'm not able to process it. Anyway...
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    [SOLVED] How to trace the original of netlist gates back to the original RTL description

    Okay ThisIsNotSam, that's what I do for know. The problem I had is with the leaf cells generated from the assign statements and muxes and stuff like that. I'm working this around by isolating each part in a separate module in order for its consumption to be visible in the PrimeTime Power...
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    [SOLVED] How to trace the original of netlist gates back to the original RTL description

    When an RTL circuit is synthesized for an ASIC technology, is to possible to trace back the original source code of the generate netlist gates? More specifically, I compiled an RTL IP using Design Compiler, and then I studied its power consumption in PrimeTime. But I saw that some modules are...
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    [SOLVED] SDF file backannotation problem: "Instance X does not have a generic named Y"

    SDF file backannotation problem: "Instance X does not have a generic named Y" After synthesizing a SystemVerilog IP in Design Compiler 2019, I exported the SDF timing backannotation file to be used in VSIM for post-synthesis simulation. However, VSIM outputs a lots of errors like this # **...
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    [SOLVED] How to evaluate the energy of an arithmetic operation

    Thank you for you answers! I actually came across something that could simplify things (since I actually have a few dozens of instructions, so running each benchmark alone will take a hell lot of time). So apparently when using the read_vcd command in PrimeTime, it is possible to specify a...
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