# [SOLVED]Typical input/output delay values

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#### noureddine-as

##### Junior Member level 2
Hi,

I'm performing ASIC synthesis, for a SystemVerilog IP, while I have a specification for the Minimum Frequency that should be supported, but I have no idea about what could be a typical input/output delay value, what are the values that are usually used in industry ?

For now I use 20% of Clock_Period for both input and output, but is it sufficient?

Code:
set_input_delay  [expr 0.2 * $CLK_PERIOD] -clock CLK_PIN [remove_from_collection [all_inputs] {CLK_PIN RESET_PIN}] set_output_delay [expr 0.2 *$CLK_PERIOD] -clock CLK_PIN [all_outputs]

#### oratie

##### Full Member level 6
As a starting point you may use 2/3 of period as input/output delay. 1/3 is for delay in your block, 1/3 - delay in another block and 1/3 is a wire/buffer delay in between two blocks.

#### noureddine-as

##### Junior Member level 2
As a starting point you may use 2/3 of period as input/output delay. 1/3 is for delay in your block, 1/3 - delay in another block and 1/3 is a wire/buffer delay in between two blocks.
I'm not sure I understood what you said, I know how to set input/output delays, but how to configure the other ones?

#### oratie

##### Full Member level 6
I've just explained 2/3 as input/output delay. We have clock period = 1/3(delay in your block) + 1/3(interblock wire/buffer delay) + 1/3(delay in another block). So, you have only 1/3 of period as allowable delay inside your block, so input/output_delay=2/3.

noureddine-as

### noureddine-as

Points: 2

#### ThisIsNotSam

if this IP is going to be later integrated in a larger SoC, you should expect to have some hints from the architect about where the data comes from and where it goes to. This is how you decide delays that are between blocks...
At the very least, you need to tell the tools that the inputs are synchronous or asynchronous to the input clock. The set_input_delay command does that indirectly.

If your block handles interfaces of the chip directly, then you need to model their timing requirements. Again, the senior architect/integrator should have the answers to these questions.

noureddine-as

### noureddine-as

Points: 2

#### noureddine-as

##### Junior Member level 2
if this IP is going to be later integrated in a larger SoC, you should expect to have some hints from the architect about where the data comes from and where it goes to. This is how you decide delays that are between blocks...
At the very least, you need to tell the tools that the inputs are synchronous or asynchronous to the input clock. The set_input_delay command does that indirectly.

If your block handles interfaces of the chip directly, then you need to model their timing requirements. Again, the senior architect/integrator should have the answers to these questions.
Indeed it's a Floating-Point Unit, and it's a research project and I don't have ideas about the orders of magnitude usually used in industry, that's why I asked the question in the first place. From the answers, it seems that it depends on where it will be used, so for a simple comparison, I'll just use what @oratie proposed.

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