Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] max_leakage_power violation when using Compile Ultra in Design Compiler

Status
Not open for further replies.

noureddine-as

Junior Member level 2
Joined
Apr 16, 2017
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
210
Hi,

I'm synthesizing an RTL block using Design Compiler, for an ASIC target. After analyzing and elaborating the design, then specifying some parameters (clock, input/output delays, operating conditions, wire model, ...) I perform compilation.

Usually I use this one:
Code:
compile -exact_map -ungroup_all
But since I needed to retime internal registers to satisfy a higher frequency constraint, plus apply clock-gating to reduce power consumption, I replaced that line with:
Code:
compile_ultra -exact_map -retime -gate_clock
However, I always get a max_leakage_power violation at the end (details below), while all the other constraints are met. Can this problem affect my future analyses? especially power analysis (in PrimeTime) in the next steps? should I worry about it? and what could I do to resolve that?
Code:
    Constraint                                       Cost
    -----------------------------------------------------
    max_transition                                 0.0000 (MET)
    max_capacitance                                0.0000 (MET)
    max_delay/setup                                0.0000 (MET)
    sequential_clock_pulse_width                   0.0000 (MET)
    critical_range                                 0.0000 (MET)
    max_leakage_power                              0.0079 (VIOLATED)
Thanks in advance.
 

oratie

Full Member level 5
Joined
Jan 10, 2007
Messages
312
Helped
161
Reputation
320
Reaction score
151
Trophy points
1,323
Activity points
3,127
Check your max_leakage_power constraint - maybe it is too tight? Do not think, that this violation may affect your future analyses. By the way, did you switch on leakage power optimization?
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
1,993
Helped
354
Reputation
708
Reaction score
350
Trophy points
83
Activity points
9,998
It only means you specified a budget for leakage that was too tight. Fix it and rerun synthesis.
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top