# [SOLVED]max_leakage_power violation when using Compile Ultra in Design Compiler

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#### noureddine-as

##### Junior Member level 1
Hi,

I'm synthesizing an RTL block using Design Compiler, for an ASIC target. After analyzing and elaborating the design, then specifying some parameters (clock, input/output delays, operating conditions, wire model, ...) I perform compilation.

Usually I use this one:
Code:
compile -exact_map -ungroup_all
But since I needed to retime internal registers to satisfy a higher frequency constraint, plus apply clock-gating to reduce power consumption, I replaced that line with:
Code:
compile_ultra -exact_map -retime -gate_clock
However, I always get a max_leakage_power violation at the end (details below), while all the other constraints are met. Can this problem affect my future analyses? especially power analysis (in PrimeTime) in the next steps? should I worry about it? and what could I do to resolve that?
Code:
    Constraint                                       Cost
-----------------------------------------------------
max_transition                                 0.0000 (MET)
max_capacitance                                0.0000 (MET)
max_delay/setup                                0.0000 (MET)
sequential_clock_pulse_width                   0.0000 (MET)
critical_range                                 0.0000 (MET)
max_leakage_power                              0.0079 (VIOLATED)

#### oratie

##### Full Member level 5
Check your max_leakage_power constraint - maybe it is too tight? Do not think, that this violation may affect your future analyses. By the way, did you switch on leakage power optimization?

noureddine-as

### noureddine-as

points: 2

#### ThisIsNotSam

It only means you specified a budget for leakage that was too tight. Fix it and rerun synthesis.

noureddine-as

### noureddine-as

points: 2

#### noureddine-as

##### Junior Member level 1

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