noureddine-as
Junior Member level 2
Hi,
I'm performing ASIC synthesis, for a SystemVerilog IP, while I have a specification for the Minimum Frequency that should be supported, but I have no idea about what could be a typical input/output delay value, what are the values that are usually used in industry ?
For now I use 20% of Clock_Period for both input and output, but is it sufficient?
I'm performing ASIC synthesis, for a SystemVerilog IP, while I have a specification for the Minimum Frequency that should be supported, but I have no idea about what could be a typical input/output delay value, what are the values that are usually used in industry ?
For now I use 20% of Clock_Period for both input and output, but is it sufficient?
Code:
set_input_delay [expr 0.2 * $CLK_PERIOD] -clock CLK_PIN [remove_from_collection [all_inputs] {CLK_PIN RESET_PIN}]
set_output_delay [expr 0.2 * $CLK_PERIOD] -clock CLK_PIN [all_outputs]