Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Is there any way to handle reset paths in encounter? I don't know how to handle this recovery and removal paths.. If i use timeDesign command, i'm getting lot of recovery and removal paths...
How to disable these reset paths???
@phoenixpavan: I'm using SOCE...
@lostinxlation: I think they must be noted in library... i wanna know the way how to find this details in lef.... ;)
@richtbiscuits: Ya, it's right. i've already seen that, It has R90. If R90 means we can rotate only 90degree or MX90, R180,270...
Hi all,
I know what is clock latency.. My question is " Assume that we are fixing the CTS with 10ns. Now we need to reduce the latency to 5ns." what should i do in design? Or what are the different way to reduce the latency? Plz reply......
I have such a lot of doubts in...
Hi,
Basically while streamout your design, You have to add the layer mapping file and some gds libraries.. And when you open with calibre also you have add some layer mapping file.. If you correct these things, then you able to see all cells and layers.
Regards,
Nantha
Hi all,
How synthesis people will desire the max transition value for design?? How to calculate that max transition for design??
[please note: I'm not asking about max transition violation.. I meant to set the max transition value before optimization]
Thanks in advance...
Hi jiancongwoo,
Please see my report... This is what i'm getting. And can u please what is command for scan chain timing report?? I can't take report for particular path...
Hi all,
I am using SOC Encounter.. I am getting some hold violation in scan chain paths.. How to solve this problem?? How to take the timing report for particular scan chain?? If I use report_timing it shows like "unconstrained path". Please give me some idea..
Thanks in advance...
Hi haykp,
I am working in Encounter. They declare every false path in Constraint file.. But my tool is not support for that false paths. That's y i am getting violation in same path what they were mention in sdc. How to solve this problem? please anyone help me..!
Rgds,
Nantha
Hi all,
Please any one help me, how to clear this slack??? Is this false path??
______________________________________________
Path 1: VIOLATED Recovery Check with Pin U5_ClkResetGen/U_ClkGenGate/EnableD1_
reg/CLK
Endpoint: U5_ClkResetGen/U_ClkGenGate/EnableD1_reg/RB (^) checked with...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
