Urgent Help: How to solve the Hold violation in scan chain???

[Nantha]

Hi all,

I am using SOC Encounter.. I am getting some hold violation in scan chain paths.. How to solve this problem?? How to take the timing report for particular scan chain?? If I use report_timing it shows like "unconstrained path". Please give me some idea..

Thanks in advance..

Rgds,
Nantha

 

[ashwinvl]

Hold violation occurs when your clock signal arrives late with respect to the data signal.. I think you need to optimize your clock tree.. At what stage of the design are you in..pre-CTS or post-CTS? "report_timing" does show the path which has timing violation. Have you given your SDC file? Just check whether your SDC file is proper..

 

[jiancongwoo]

Hi Nantha,
first of all, you need to check the clock skew in scan mode, if skew is ok, then you need to check whether this violation is true or not, ex: scan path should end at scan in pin of a flop.
if both of them are ok, you need to check the location density, if density is ok, fixing hold violation is very easy!

 

[Nantha]

Hi jiancongwoo,

Please see my report... This is what i'm getting. And can u please what is command for scan chain timing report?? I can't take report for particular path..


----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Path 1: VIOLATED Hold Check with Pin U_I2CSlave/U_RegControl/ClearTstBit0_reg/CLK
Endpoint: U_I2CSlave/U_RegControl/ClearTstBit0_reg/DATA (v) checked with leading edge of 'SCANCLK'
Beginpoint: U_I2CSlave/U_I2CSlaveCore/ClearTstBit_reg/Q (v) triggered by leading edge of 'SCANCLK'
Other End Arrival Time 571.138
+ Hold -2.700
+ Phase Shift 0.000
- CPPR Adjustment 11.481
= Required Time 556.957
Arrival Time 504.397
Slack Time -52.560
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
-----------------------------------------------------------------------------------------------------------------------------------
Cell Net Instance Arc Delay Slew Arrival Time Incr Delay
-----------------------------------------------------------------------------------------------------------------------------------
TESTIN[0] TESTIN[0] ^ 1.000 0.000
SCWBUFXH1 TESTIN_0_N_buf
TESTIN_0_I_buf A ^ -> Y ^ 78.958 139.300 78.958 0.000
SCVAND2XH1 SCANCLK U_ScanMux/p214748365A6894
A ^ -> Y ^ 92.774 59.300 171.732 0.000
SCVMUX2XC1 U5_ClkResetGen/ClkFreeMuxOut
U5_ClkResetGen/U_ClkFreeScMux
D1 ^ -> Y ^ 51.851 38.200 223.583 0.000
SCVFBUFCLXR1 ClkFree U5_ClkResetGen/U_ClkFreeBuff
A ^ -> Y ^ 22.698 15.000 246.281 0.000
SCVFBUFCLXR1 ClkFree__L1_N1
ClkFree__L1_I1 A ^ -> Y ^ 72.909 120.600 319.190 0.000
SCVFBUFCLXL1 ClkFree__L2_N17
ClkFree__L2_I17 A ^ -> Y ^ 81.097 82.700 400.287 0.000
SCWSDFFQRBXAA U_I2CSlave/ClearTstBit
U_I2CSlave/U_I2CSlaveCore/ClearTstBit_reg
CLK ^ -> Q v 103.310 44.100 503.597 0.000
SCWSDFFQRBXC1 U_I2CSlave/U_RegControl/ClearTstBit0_reg
DATA v 0.800 44.100 504.397 0.000
-----------------------------------------------------------------------------------------------------------------------------------

 

[chiplogic]

There is no separate command for scan chain timing report.The timing report will be generated based on your sdc.
Make sure CTS delay for both launch and capture path is almost same.
Or adjust the skew between lauch and capture path to meet hold or add buffers near to endpoint to meet HOLD.
Between can you upload full report with " -path_type full_clock" option in report timing

 

[jiancongwoo]

Hi Nantha
do as chiplogic told you to do.

this problem is very easy. trust me.