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Recent content by manikanta.9332

  1. M

    Can a single port have multi-clocked

    Hai all, Can a single port have multi-clocked? How do you set delays for such ports? Thanks.............
  2. M

    do you need to constrain all IO (Input-Output) ports

    Hai all, In building the timing constraints, do you need to constrain all IO (Input-Output) ports? Thanks...............
  3. M

    No of Technologies and present technology

    Hai all, pleace list the From 180um to 28nm technologies? Thanks.
  4. M

    Netlist formats ........

    Hai all, IN .V format what are presents? In .ddc format What are present? With Out logical connectivity of Cell.. what is the diffrence between .v and .ddc? Thanks....
  5. M

    Asynchronous signal................

    Hai all, clock generators are oscillator and PLL. like What are Asynchronous signal generators ? Thanks......
  6. M

    Asynchronous signal................

    Hai all, Where Asynchronous signal generates? Thanks..........
  7. M

    Recovery,Removal Check........

    Hai all, What is Recovery Check,Removal Check? please could u tell me Eqs for Recovery check,Removal Check like setup time and Hold time ? Thank u............
  8. M

    scan chain insertion

    Thanks.... scan flipflop means normal flip flop it having D,si,test clok,funtonal clock are giving with help of mux ?. or scan flipflop mean it has si,so,test clok,funtonal clock pin ? thanks
  9. M

    scan chain insertion

    Hi all, Scan chain insertion meant what? We are adding any flipflops or any mux in the design ? scan chain means what we are addind ? Thanks.......
  10. M

    Explain power cells .......

    Hai all, what is meant by power cells? why these are using? Thanks.................
  11. M

    Explain Power Gating

    Thanks... Hai all, Any special cells are using for power gating? Thanks...
  12. M

    Explain Power Gating

    Hai all, What are the power gating cells? what is the structure of power gating cells? Thanks...........
  13. M

    recovery time & removal time

    Thanks.................
  14. M

    design rule constraints

    Hai, In Which steps Logical DRCs are performing? Thanks........
  15. M

    recovery time & removal time

    Hai all, what is the difference between recovery time & removal time? Where we are we are using these ? What is the advantage of these both? Thanks.......
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