Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

design rule constraints

Thread starter manikanta.9332
Start date Feb 28, 2013

Status: Not open for further replies.

Feb 28, 2013

#1

M

manikanta.9332

Member level 3

Member level 3

Hai,

In Which steps Logical DRCs are performing?

Thanks........

Status: Not open for further replies.

Similar threads

L
Conformal HDL Rule checks
- Started by Learner12
- Oct 22, 2024
- Replies: 1
ASIC Design Methodologies and Tools (Digital)
Q
SPI timing constraints
- Started by Qwerty112233
- Mar 12, 2024
- Replies: 3
ASIC Design Methodologies and Tools (Digital)
Q
timing constraints for bidirectional IO pads
- Started by Qwerty112233
- Jan 30, 2024
- Replies: 0
ASIC Design Methodologies and Tools (Digital)
Q
Writing timing constraints for clock divider
- Started by Qwerty112233
- Oct 14, 2023
- Replies: 0
ASIC Design Methodologies and Tools (Digital)
A
master clock and generated clock constraints
- Started by Ashokb431
- Jul 26, 2023
- Replies: 1
ASIC Design Methodologies and Tools (Digital)

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top