Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Explain Power Gating

Status
Not open for further replies.

manikanta.9332

Member level 3
Joined
Mar 29, 2012
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Banglore
Activity points
1,614
Hai all,


What are the power gating cells?

what is the structure of power gating cells?

Thanks...........
 

Prashanthanilm

Full Member level 5
Joined
Aug 24, 2012
Messages
303
Helped
36
Reputation
72
Reaction score
36
Trophy points
1,308
Activity points
2,950
Power gating cells are used to save power consumption.

The technique is to stop the flow of current to those circuit which are currently not in use. Thereby reducing leakage.

Don't know about structure of power gating cells. I think the widths will be more comparatively.
 

rca

Advanced Member level 4
Joined
May 20, 2010
Messages
1,485
Helped
355
Reputation
710
Reaction score
328
Trophy points
1,363
Location
Marin
Activity points
8,522
The gate is to avoid propagation of combinational signal through the combinational logic.
The gating could be on clock signal or on data signal.

The power gating is to switch off/on some part of the logic, which include combinational or flops elements. To restart there is to possibility, first using flop with two power consumption to preserve the contain when the power is off, the second solution, the contain is lost and you must properly "restart" with reset or reload structure.
 

Prashanthanilm

Full Member level 5
Joined
Aug 24, 2012
Messages
303
Helped
36
Reputation
72
Reaction score
36
Trophy points
1,308
Activity points
2,950
The power gating is to switch off/on some part of the logic, which include combinational or flops elements. To restart there is to possibility, first using flop with two power consumption to preserve the contain when the power is off, the second solution, the contain is lost and you must properly "restart" with reset or reload structure.

Can you explain this above statement? Its not clear.

So, gate is used to avoid the passage of signal when not required. right?
 

siddarth.ghaste

Advanced Member level 4
Joined
Feb 5, 2013
Messages
109
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Location
Bengaluru,Karnataka,INDIA
Activity points
1,911
yes...some parts may not be necessary in some application.for EX, clock is given to F/F through AND gate with Enable and clock as two inputs.When you don't need F/F to perform some action then you disable the Enable pin,by this time F/F will not get clock,So it will not make any transition, so it will not use any power.
 
Last edited:

rca

Advanced Member level 4
Joined
May 20, 2010
Messages
1,485
Helped
355
Reputation
710
Reaction score
328
Trophy points
1,363
Location
Marin
Activity points
8,522
The power gating is to save leakage power on part which could be switch off.
That's mean, you need to have some power switchs. For small node below 65nm, some std cell library provided the power switch required for that, or you need to develope your own power switch. This power switch will provided the power for the/some std cell rows.
You need to think about the power-on procedure, I means, you should need multiple power switch to be able to drive enough current, then do you power on all power switch at the same time, or one by one...?
Also this std cell library provide some flop with retention. That's mean this flop have two power supply, one to save the contain when the power switch cut the power, and the second power supply for the functional mode. Then, you need to define which module or flop need to save it contain during the power-off state, or to define a power procedure with reload state...
It is not very direct to add this feature, and that used some area, and after that, the software need to be aware, of stabillisation time when power switch is on...
....
 

manikanta.9332

Member level 3
Joined
Mar 29, 2012
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Banglore
Activity points
1,614
Thanks...

Hai all,


Any special cells are using for power gating?

Thanks...
 

mail4idle2

Full Member level 4
Joined
Oct 20, 2012
Messages
200
Helped
20
Reputation
40
Reaction score
19
Trophy points
1,298
Activity points
2,173
There are no power gating cells. Power Gating is a design practice
 

artmalik

Full Member level 5
Joined
Mar 13, 2013
Messages
255
Helped
91
Reputation
182
Reaction score
87
Trophy points
1,308
Location
San Diego
Activity points
2,997
Power gating simply means to cut off design using an Nmos or pmos as switches. These are basically a single nmos or pmos cells in standard cell library. The key fact to take care of in this.
a) Power gating switch should be wide enough to sink or source sufficient current during the functional mode.
b) The Vt of the power switch is usually high compared to logic gates it is trying to gate off to justify the saving in leakage.
c) As mentioned above you will need as power supply to control the power for the buffers which will turn off/on the power gates.
d) Surge current : as there will be many gates which will turn off or on due to power gates, it is important you do spice simulations to make sure the amount of current flowing through the power gate doesnt draw in-ordinate amount of current.
e) Power gating cells are put in the std cells rows in a "diamond" shape before the rest of the logic is put.
f) also one has to be carefully which power gate design interacts with non-power gated design due to floating inputs. they need to have isolation cells.


There are no power gating cells. Power Gating is a design practice
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top