Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,All,
There is an OTP cell in my chip, which is an IP, and will be merged by foundry, so
I can not get GDS or netlist of OTP, except an empty layout instance with only top metal.
How can I ensure the correctness of LVS? I have tried, and if I connected the OTP wrongly in purpose,
LVS can...
Hi,
I need a DAC which changes with the step of 0.5dB. At present, i have no idea of how to design it . please give me some suggestion or paper links.
Thanks in advance!
The load of BGR is a swithed cap, about 2MHz. In my simulation, vref has enough time to settle in one cycle, so there is little droop. However, the droop has any relationship with Power ramping up?
pls give me furter suggestion! thanks!
Hi,
In lab, i have tested the chip with an bandgap, but the results confused me. when power supply ramps up, the output of bandgap will go down gradually.and this issue only happens when ADC begins to work. In only bandgap working mode,bandgap output is constant with power supply ramping up...
Dear all,
I have some problem on high speed buffer design, in which a big cap is used to get a low impedance at high frequency. what bother me is that there is a drift in transient simulation from DC value of reference output. I try to minimize the output impedance of opamp to reduce the...
200410cicc_vrefdesign
Hi all,
I wanna get a 2.5Volt output with a power supply of 3.3Volt. Because i give a cascode as the output stage of buffer, the combination of Amp and 2 resistors can not be used (because of the saturation requirement of cascode and power supply variation 2.7~3.3V)...
Thanks, albert22.
As what you said ,i should first sweep controlling voltage of VCO,and then
find one voltage corresponding to the center frequency(½(fmax+fmin)),which is
the controlling voltage when PLL is in lock-state . is it true ?
Center frequency in vco is the frequency when control-voltage from loop filter equals to zero,or when the voltage-difference over varator equals to zero?
if the first answer is right ,does it mean that center frequency is the lowest frequency in VCO or pll?
hello,
I meet some problems in vco simulation.
(1)how can i get the curve of frequency or varactor capacitance versus tuning voltage in spectreRF? especially the curve of varactor capacitance vs tuning voltage.without it ,i don`t know the value of varactor in given controlling voltage,so i...
hi,Grig:
I have tried to produce a GDSII first deriving form ADS layout tool,and then import it into ADS.
it`s ok ,and i can get the layout from the GDSII .
but i still can`t import GDSII derived form virtuoso into ADS.
Is it the problem of layer definitions between virtuoso and ADS?
pls...
I make the spiral inductor layout in virtuoso, and i need import the layout
into @DS-momentum in pc.
I outport the layout from cadence into GDSII , but @DS doesn`t identify the GDSII file when imported into @DS.
how can i figure it out ?
By the way i want to use momentum in @DS to...
I make the spiral inductor layout in virtuoso, and i need import the layout
into @DS-momentum in pc.
I outport the layout from cadence into GDSII , but @DS doesn`t identify the GDSII file when imported into @DS.
how can i figure it out ?
By the way i want to use momentum in ADS to model...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
