Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

a question about center frequency in VCO

Status
Not open for further replies.

lotoy

Member level 1
Member level 1
Joined
Jun 2, 2005
Messages
32
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,513
Center frequency in vco is the frequency when control-voltage from loop filter equals to zero,or when the voltage-difference over varator equals to zero?

if the first answer is right ,does it mean that center frequency is the lowest frequency in VCO or pll?
 

I would rather think of the center freq as the middle of the band covered by the VCO. That is in the center of Fmin and Fmax. The voltage of the VCO shoul be on the middle of its range (if it is linear)
 

Thanks, albert22.

As what you said ,i should first sweep controlling voltage of VCO,and then

find one voltage corresponding to the center frequency(½(fmax+fmin)),which is

the controlling voltage when PLL is in lock-state . is it true ?





albert22 said:
I would rather think of the center freq as the middle of the band covered by the VCO. That is in the center of Fmin and Fmax. The voltage of the VCO shoul be on the middle of its range (if it is linear)
 

lotoy
The pll will vary the voltage out of the loop filter and into the vco, until the required freq is reached (indicated by the phase comp). In this condition the pll is locked.
If you intend to adjust a pll whose operating range is fmin to fmax.
First you should check that the VCO can go from fmin to fmax over the range of voltages of the loop filter (VCO input). To check it. Set the divider for the lowest freq and see if the pll locks. Then repeat for the highest freq. When the pll is locked you can measue the vco voltage with a high impedance voltmeter.
If you cannot lock the pll then you must adjust the value of the C or L on the VCO.
And repeat the process to ensure that the pll will lock on the limits and hence on all the operating band.
The voltages for fmin and fmax must be near to the limits of the loop filter but with enough tolerance to take into account variations in temperature, supply voltage, loading of the osc, etc.

To check the VCO (open loop) you can connect a potentiometer to the VCO control voltage and a freq meter to the output and plot the VCO response.

I assumed that you are talking about a programmable pll (freq synthesizer). If your pll does not have a programmable divider. just give me more details.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top