Injection locked VCO

[Sunny_]

Hello everyone,

I am trying to design an injection-locked VCO for the 2.45GHz band. First, I want to have a working design and then try to improve the output power and phase noise. I want to build the IL-VCO on PCB, not in IC.
During my research on the internet, I did find only one design which is at the same time VCO and with an injection port but I was not able to reproduce it in simulation... The illustration of this design is shown below. The annonced output power is 10dBm with 0.3GHz bandwith.

I am wondering if anyone have an idea on how to do so and also if anyone could enlight me in the difference with BJT or FET for oscillators at 2.45GHz. I was able to do a injection-locked oscillator using Ansys circuit but the output voltage is very low (10mV) but I could not replicate this result using LTspice or Qucs using the same schematic..

Thank you,

 

[Sunny_]

Sorry to backup the post but I am trying a last time to get advice on this circuit. I can delete the post it if it is not allowed on this forum to do so.

What I did for this oscillator is first choose a RF JFET reference and simulated it to check if IV curves match the datasheet. Then I simulated a complete EVB for LNA application and validated this with results from the datasheet EVB. So for me the model is validated.
Then I started the oscillator design. I set a bias for the FET. I only considered L_choke and resistors and removed all Ci, Cs, Cd, Ld. I set a bias to 35mA which is the double of the wanted current on the 50ohm load output for the wanted power. I verified maximum current allowed for the FET which is 60mA.
After that, my prodecure to design the oscillator was :

1. Add C0 and Cd as decoupling capacitors and add S_port behind them. I expected to see |S21|>0dB with port 1 on Cd side and port 2 on output.
2. Then I add the Cs1, Cs2. I expected to see Z11 on the capacitive side of the smith chart and |S11|>0dB for oscillation.
3. Lastly, I had the LC tank Ct and Ld. I vary Ld to have a phase of 0° on S11 at 2.45GHz as well as |S11|>0dB

By doing so, I never get |S21|>0dB from step 1 nor others steps. I also tried to add the 50ohm load on injection port. Without it, I see a floating gate for the JFET in small signals and was not sure about this.
Is my procedure to design the oscillation wrong ? Can JFET stability impact the oscillation ?

 

[biff44]

well, basically you can injection lock an oscillator a LOT of ways. back in the day we would use a ferrite circulator to separate the oscillator output power vs the injected input power
My concern on your diagram is: what is the IMPEDANCE Zl that the gate of the FET sees looking out?

As you might imagine, loading the gate of the fet with any old impedance will change the phase shift of the device as it tries to amplify signals, and as such will "load pull" the operating frequency.

In the simpest case, for your circuit, i would make the capacitor Ci be really tiny! i.e. make it be -J200 ohms or so. that way the high capacitive reactance isolates the fet gate from the injection part of the circuit, and it will behave in a repeatable fashion.
you WILL need to drive the injection power a little higher, since much of it gets reflected at the Ci.

 

[Sunny_]

Thank you biff44 for your reply !

I followed this design that I found in several papers. It is said that the high impedance at the JFET gate is why the injection is placed there and why a JFET is used and not a BJT or MOSFET. Injection port is typically 50ohm. At the moment, I am trying to achieve the oscillator part without considering the injection process.

The circuit is not common source or common drain amplifier since LC tank (input) is on drain and output on drain. This circuit is not common and I have difficulties achieving the oscillating part. I did the procedure of my previous message as I can do for a common Clapp oscillator but the LC tank and output being on drain and source make it not working for me yet. I tried to compute the transistor gain in small signals but since I do not consider injection port at 50ohm, the gate is left floating which is strange for me.

Here is an example of my research without 50ohm on injection port :
I achieved the JFET bias and add port 1 and 2 as my previous post. I expect |S21|>0dB and negative resistance before going to step 2.
What I see is |S21|<0dB (which is wrong for me). However, I do have |S12|>0dB and a negative impedance there.

I made sure that the papers are connecting output on port 2 and not port1. Also, I tried to continue my procedure design by changing the LC tank and output position but as soon as I add Cs1 and Cs2, the negative impedance disappear..

If you have an idea, I would be very happy to hear it. I can let you know for the injection process when the oscillating part is working for me !
For the moment, I do not really understand what is wrong with my design