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Recent content by lever

  1. L

    which language is better between SystemC and System Verilog?

    Are there any good reference books about the system verilog ?
  2. L

    How can I understand the delay in verilog lib file

    Yes, I can understand lib file. But I don't know why the difference between the information of lib file and specify timing information in the verilog simulation lib file. It's miraculous
  3. L

    negative setup and hold

    The normal case is that the data must be hold "hold time" after clk edge. And the negative hold time means the data can changed before the clk edge. Some blocks may have the negative hold time because they may have the special circuit to hold the data inside.
  4. L

    How can I understand the delay in verilog lib file

    for example, the OAI112 `resetall `timescale 10ps/1ps `celldefine module OAI112(O, A1, B1, C1, C2); output O; input A1, B1, C1, C2; //Function Block `protect or g1(o1, C1, C2); nand g2(O, A1, B1, o1); //Specify Block specify // Module Path Delay if (C1 == 0 && C2...
  5. L

    Multi channel digital switch design,need help!

    the CPLD maybe the better for your simple design. you need not download each time or add flash chip.
  6. L

    Does the "network on chip" belongs to this forum?

    I am studying the proiect about "network on chip". where it is suitable to ask some questions about circuit design and system design?
  7. L

    difference between clock buffer and ordinary buffer

    clock buffer is optimized for some requirements of clock especially. (skew, power and so on) The clock buffer is symmetrical cell. It means the rise delay equal fall delay nearly.
  8. L

    What is the basic things you need for doing synthesis in VHDL?

    Re: Synthesis you must design the netlist (like VHDL) And you must have the synthesis tool. It can not be waived. Of course, you need have the ability to use the tool :)
  9. L

    Native testbench and System Verilog

    Re: **SYSTEM VERILOG** Who can compare System C and System Verilog? which is better for testbench?
  10. L

    Booth algorithm hardware implementation

    booths algorithm hardware here is the tutorial file which I write for undergraduate students. It maybe able to help you. If you need the verilog file, I also can find it and upload it.
  11. L

    which language is better between SystemC and System Verilog?

    I want to design the simulation platform for one asynchronous system. Because the system is complex, verilog or VHDL can not express clear and has no enough run speed. But I find the system C is not good for asynchronous circuit. How can I simulate asynchronous system by systemC very well? And...
  12. L

    what's the difference betw. SRAM & register file?

    sram vs register file Does it mean that register file is the optimization from SRAM? And if I want to use 1kbit FIFO, which type of the memory array is better ?
  13. L

    Comparison of Perl and Tcl script languages

    perl vs. tcl Perl is more professional than TCL. And Perl can handle more things. But TCL is more used in the EDA tools directly and Perl need run individually.
  14. L

    Synopsys DC: explain to me DC-TCI command

    Synopsys DC In the synopsys install directory, you can find the turorial and ref books. Or you can get them from web.
  15. L

    Documents for learning Matlab

    matlab I think matlab is not difficult to learn. Use a tutorial for beginner to learn at first and try some simple examples.
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