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which language is better between SystemC and System Verilog?

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lever

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I want to design the simulation platform for one asynchronous system. Because the system is complex, verilog or VHDL can not express clear and has no enough run speed.
But I find the system C is not good for asynchronous circuit. How can I simulate asynchronous system by systemC very well?
And I am not familiar with System Verilog. Also I can not find good documents to study System Verilog.
Is System C or System Verilog better?
 

dumeHCM

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Re: which language is better between SystemC and System Veri

System Verilog is better
 

dumeHCM

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Re: which language is better between SystemC and System Veri

Base on the number of Books and Publications
 

lever

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Are there any good reference books about the system verilog ?
 

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